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zilog worldwide headquarters ? 532 race street ? san jose, ca 95126-3432 telephone: 408.558.8500 ? fax: 408.558.8300 ? www.zilog.com product specification ps023806-0506 z8 gp tm microcontrollers zgp323h otp mcu family
disclaimer ps023806-0506 this publication is subject to replacement by a la ter edition. to determine whether a later edition exists, or to request copies of publications, contact: zilog worldwide headquarters 532 race street san jose, ca 95126-3432 telephone: 408.558.8500 fax: 408.558.8300 www. zilog .com zilog is a registered trademark of zilog inc. in the unit ed states and in other countri es. all other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. document disclaimer ?2005 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible us es and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not a ssume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. devi ces sold by zilog, inc. are covered by warranty and limitation of liability provisions a ppearing in the zilog, inc. terms and conditions of sale. zilog, inc. makes no warranty of merchantability or fitness for any purpose. e xcept with the express writt en approval of zilog, use of information, devices, or technology as critical components of life support syst ems is not authorized. no licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
zgp323h product specification ps023806-0506 revision history iii revision history each instance in the revision history table reflects a change to this document from its previous revision. for more deta ils, refer to the corresponding pages or appropriate link in the table below. date revision level section description page no. december 2004 02 changed low power consumption, stop and halt mode current values, deleted mask option note, clarified temperature ranges in tables 6 and 8 and 10. added new tables 9 and 10. also added characterization data to table 11 and changed program/erase endurance value in table 12. 1,2,10 11,12, 13,14, 15 removed preliminary designation all march 2005 03 minor change to table 9 electrical characteristics. added 20, 28 and 40- pin cdip parts in the ordering section. 11,90 october 2005 04 updated ?ordering information? on page 90. november 2005 05 updated ?ordering information? on page 90, added caution for i/o ports 0, 1 and 2 on pages 18 and 19, and added new clock information on pages 54 and 55. may 2006 06 added pin 22 to smr block input, figure 33 . 53
zgp323h product specification ps023806-0506 table of contents iv table of contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 development features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 xtal1 crystal 1 (time-based input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 xtal2 crystal 2 (time-based output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 reset (input, active low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 expanded register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 counter/timer functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 expanded register file control registers (0d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 expanded register file control registers (0f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 standard control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
zgp323h product specification ps023806-0506 table of contents v packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 document number description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
zgp323h product specification ps023806-0506 list of figures v list of figures figure 1. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. counter/timers diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. 20-pin pdip/soic/ssop/cdip* pin configuration . . . . . . . . . . . . . . . . . . . 5 figure 4. 28-pin pdip/soic/ssop/cdip* pin configuration . . . . . . . . . . . . . . . . . . 6 figure 5. 40-pin pdip/cdip* pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. 48-pin ssop pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. port 0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. port 1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. port 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. port 3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. port 3 counter/timer output configuratio n . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 12. program memory map (32 k otp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13. expanded register file architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. register pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 15. register pointer?detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 16. glitch filter circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 17. transmit mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 18. 8-bit counter/timer circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 19. t8_out in single-pass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 20. t8_out in modulo-n mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 21. demodulation mode count capture flowch art . . . . . . . . . . . . . . . . . . . . . . 38 figure 22. demodulation mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 23. 16-bit counter/timer circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 24. t16_out in single-pass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 25. t16_out in modulo-n mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 26. ping-pong mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 27. output circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 28. interrupt block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 29. oscillator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 30. port configuration register (pcon) (write only) . . . . . . . . . . . . . . . . . . . 49 figure 31. stop mode recovery register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 32. sclk circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 33. stop mode recovery source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 34. stop mode recovery register 2 ((0f)dh:d2?d4, d6 write only) . . . . . . 55 figure 35. watch-dog timer mode register (write only) . . . . . . . . . . . . . . . . . . . . . 56
zgp323h product specification ps023806-0506 list of figures vi figure 36. resets and wdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 37. tc8 control register ((0d)o0h: re ad/write except where noted) . . . . . 60 figure 38. t8 and t16 common control functio ns ((0d)01h: read/write) . . . . . . . . 61 figure 39. t16 control register ((0d) 2h: re ad/write except where noted) . . . . . . 62 figure 40. t8/t16 control register (0d)03h: read/write (except where noted) . . . 63 figure 41. voltage detection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 42. port configuration register (pcon)(0 f)00h: write only) . . . . . . . . . . . . 65 figure 43. stop mode recovery register ((0f)0bh: d6?d0=write only, d7=read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 44. stop mode recovery register 2 ((0f)0dh:d2?d4, d6 write only) . . . . . 66 figure 45. watch-dog timer register ((0f) 0fh: write only) . . . . . . . . . . . . . . . . . . 67 figure 46. port 2 mode register (f6h: write only) . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 47. port 3 mode register (f7h: write only) . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 48. port 0 and 1 mode register (f8h: write only) . . . . . . . . . . . . . . . . . . . . . 69 figure 49. interrupt priority register (f9h: write only) . . . . . . . . . . . . . . . . . . . . . . . 70 figure 50. interrupt request register (fah: read/write) . . . . . . . . . . . . . . . . . . . . . . 70 figure 51. interrupt mask register (fbh: read/write ) . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 52. flag register (fch: read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 53. register pointer (fdh: read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 54. stack pointer high (feh: read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 55. stack pointer low (ffh: read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 56. test load diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 57. ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 58. 20-pin cdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 59. 20-pin pdip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 60. 20-pin soic package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 61. 20-pin ssop package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 62. 28-pin soic package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 63. 28-pin cdip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 64. 28-pin pdip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 65. 28-pin ssop package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 66. 40-pin pdip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 67. 40-pin cdip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 68. 48-pin ssop package design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
zgp323h product specification ps023806-0506 list of tables viii list of tables table 1. power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 3. 20-pin pdip/soic/ssop/cdip* pin identif ication . . . . . . . . . . . . . . . . . . . 5 table 4. 28-pin pdip/soic/ssop/cdip* pin identif ication . . . . . . . . . . . . . . . . . . . 6 table 5. 40- and 48-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. port 3 pin function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7. ctr1(0d)01h t8 and t16 common functions . . . . . . . . . . . . . . . . . . . . . 29 table 8. interrupt types, sources, and vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 9. irq register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 10. smr2(f)0dh:stop mode recovery register 2* . . . . . . . . . . . . . . . . . . . . 52 table 11. stop mode recovery source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 12. watch-dog timer time select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 13. eprom selectable options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 14. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 15. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 16. gp323hs dc characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 17. gp323he dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 18. gp323ha dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 19. eprom/otp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 20. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
zgp323h product specification ps023806-0506 architectural overview 1 architectural overview the zgp323h is an otp-based member of th e mcu family of infrared microcontrollers. with 237 b of general-purpose ram and up to 32 kb of otp, zilog?s cmos microcontrollers offer fast-executing, effici ent use of memory, soph isticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up transistors. the zgp323h architecture ( figure 1 ) is based on zilog?s 8-bit microcontroller core with an expanded register file allowing access to register-mapped peripherals, input/ output (i/o) circuits, and powerfu l counter/timer circuitry. the z8 ? offers a flexible i/o scheme, an efficient register and address sp ace structure, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery- operated hand-held applications. there are three basic address spaces available to support a wide range of configurations: program memory, register file and expanded re gister file. the register file is composed of 256 bytes of ram. it includes 4 i/o port regi sters, 16 control and status registers, and 236 general-purpose registers. the expanded register file consists of two additional register groups (f and d). to unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodula ting complex waveform/pulses, the z8 gp otp offers a new intelligent counte r/timer architecture with 8-bit and 16-bit counter/timers (see figure 2 ). also included are a large number of user-selectable modes and two on-board comparators to proc ess analog signals with separate reference voltages. all signals with an overline, ? ?, are active low. for example, b/w , in which word is active low, and b /w, in which byte is active low. power connections use the conven tional descriptions listed in table 1 . table 1. power connections connection circuit device power v cc v dd ground gnd v ss note:
zgp323h product specification ps023806-0506 architectural overview 2 development features table 2 lists the features of zilog?s zgp323h members. ? low power consumption?18 mw (typical) ? t = temperature s = standard 0 cto +70 c e = extended -40 c to +105 c a = automotive -40 c to +125 c ? three standby modes: ? stop? (typical 1.8 a ) ? halt? (typical 0.8 ma) ? low voltage reset ? special architecture to automate both ge neration and reception of complex pulses or signals: ? one programmable 8-bit counter/timer wi th two capture registers and two load registers ? one programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair ? programmable input glitch filter for pulse reception ? six priority interrupts ? three external ? two assigned to counter/timers ? one low-voltage detection interrupt ? low voltage detection and hi gh voltage detection flags ? programmable watch-dog timer/power-on reset (wdt/por) circuits ? two independent comparators with programmable interrupt polarity ? programmable eprom options table 2. features device otp (kb) ram (bytes) i/o lines voltage range zgp323h otp mcu family 4, 8, 16, 32 237 32, 24 or 16 2.0 v?5.5 v
zgp323h product specification ps023806-0506 architectural overview 3 ? port 0: 0?3 pull-up transistors ? port 0: 4?7 pull-up transistors ? port 1: 0?3 pull-up transistors ? port 1: 4?7 pull-up transistors ? port 2: 0?7 pull-up transistors ? eprom protection ? wdt enabled at por functional block diagram figure 1 illustrates the zgp323h mc u functional block diagram. figure 1. functional block diagram z8? core port 2 port 0 p21 p22 p23 p24 p25 p26 p27 p20 i/o bit programmable p04 p05 p06 p07 p00 p01 p02 p03 i/o nibble programmable register file 256 x 8-bit register bus internal address bus internal data bus expanded register file expanded register bus z8 ? core counter/timer 8 8-bit counter/timer 16 16-bit v dd v ss xtal reset pref1/p30 p31 p32 p33 p34 p35 p36 p37 port 3 machine timing & instruction control power 4 4 otp up to 32k x 8 port 1 p14 p15 p16 p17 p10 p11 p12 p13 i/o byte programmable 8 watch-dog timer low voltage detection high voltage detection 2 comparators note: refer to the specific package for available pins. power-on reset
zgp323h product specification ps023806-0506 architectural overview 4 figure 2. counter/timers diagram hi16 lo16 16-bit t16 tc16h tc16l hi8 lo8 and/or logic clock divider glitch filter edge detect circuit 8-bit t8 tc8h tc8l 8 8 16 8 input sclk 1 2 48 timer 16 timer 8/16 timer 8 8 8 8 8 8
zgp323h product specification ps023806-0506 pin description 5 pin description the pin configuration fo r the 20-pin pdip/soic/ssop is illustrated in figure 3 and described in table 3 . the pin configuration for the 28-p in pdip/soic/ssop are depicted in figure 4 and described in table 4 . the pin configurations for the 40-pin pdip and 48-pin ssop versions are illustrated in figure 5 , figure 6 , and described in table 5 . for customer engineering code development, a uv eraseable windowed cerdip packaging is offered in 20-pin, 28-pin , and 40-pin configurations. zilog does not recommend nor guarantee these packages for use in production. figure 3. 20-pin pdip/soic/ssop/cdip* pin configuration table 3. 20-pin pdip/soic/ ssop/cdip* pin identification pin # symbol function direction 1?3 p25?p27 port 2, bits 5,6,7 input/output 4 p07 port 0, bit 7 input/output 5v dd power supply 6 xtal2 crystal oscillator clock output 7 xtal1 crystal oscillator clock input 8?10 p31?p33 port 3, bits 1,2,3 input 11,12 p34. p36 port 3, bits 4,6 output 13 p00/pref1/p30 port 0, bit 0/analog reference input port 3 bit 0 input/output for p00 input for pref1/p30 p25 p26 p27 p07 v dd xtal2 xtal1 p31 p32 p33 p24 p23 p22 p21 p20 v ss p01 p00/pref1/p30 p36 p34 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20-pin pdip soic ssop cdip*
zgp323h product specification ps023806-0506 pin description 6 figure 4. 28-pin pdip/soic/ssop/cdip* pin configuration 14 p01 port 0, bit 1 input/output 15 v ss ground 16?20 p20?p24 port 2, bits 0,1,2,3,4 input/output table 4. 28-pin pdip/soic/ ssop/cdip* pin identification pin symbol direction description 1-3 p25-p27 input/output port 2, bits 5,6,7 4-7 p04-p07 input/output port 0, bits 4,5,6,7 8v dd power supply 9 xtal2 output crystal, oscillator clock 10 xtal1 input crystal, oscillator clock 11-13 p31-p33 input port 3, bits 1,2,3 14 p34 output port 3, bit 4 15 p35 output port 3, bit 5 16 p37 output port 3, bit 7 17 p36 output port 3, bit 6 18 pref1/p30 port 3 bit 0 input analog ref input; connect to v cc if not used input for pref1/p30 table 3. 20-pin pdip/soic/ssop/cd ip* pin identification (continued) pin # symbol function direction p24 p23 p22 p21 p20 p03 v ss p02 p01 p00 pref1/p30 p36 p37 p35 p25 p26 p27 p04 p05 p06 p07 v dd xtal2 xtal1 p31 p32 p33 p34 1 28-pin pdip soic ssop 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cdip*
zgp323h product specification ps023806-0506 pin description 7 figure 5. 40-pin pdip/cdi p* pin configuration *windowed cerdip. these units are intended to be used for engineering code development only. zilog does not recommend/guaran tee this package for production use. 19-21 p00-p02 input/output port 0, bits 0,1,2 22 v ss ground 23 p03 input/output port 0, bit 3 24-28 p20-p24 input/output port 2, bits 0-4 table 4. 28-pin pdip/soic/ssop/cd ip* pin identification (continued) pin symbol direction description nc p25 p26 p27 p04 p05 p06 p14 p15 p07 vdd p16 p17 xtal2 xtal1 p31 p32 p33 p34 nc nc p24 p23 p22 p21 p20 p03 p13 p12 vss p02 p11 p10 p01 p00 pref1/p30 p36 p37 p35 reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 39 28 27 26 25 24 23 22 21 40-pin pdip cdip* note:
zgp323h product specification ps023806-0506 pin description 8 figure 6. 48-pin ssop pin configuration table 5. 40- and 48-pin configuration 40-pin pdip # 48-pin ssop # symbol 26 31 p00 27 32 p01 30 35 p02 34 41 p03 55 p04 67 p05 78 p06 10 11 p07 28 33 p10 29 34 p11 32 39 p12 nc p25 p26 p27 p04 n/c p05 p06 p14 p15 p07 vdd vdd n/c p16 p17 xtal2 xtal1 p31 p32 p33 p34 nc vss nc nc p24 p23 p22 p21 p20 p03 p13 p12 vss vss n/c p02 p11 p10 p01 p00 n/c pref1/p30 p36 p37 p35 reset 48-pin ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
zgp323h product specification ps023806-0506 pin description 9 33 40 p13 89 p14 910p15 12 15 p16 13 16 p17 35 42 p20 36 43 p21 37 44 p22 38 45 p23 39 46 p24 22 p25 33 p26 44 p27 16 19 p31 17 20 p32 18 21 p33 19 22 p34 22 26 p35 24 28 p36 23 27 p37 20 23 nc 40 47 nc 11 nc 21 25 reset 15 18 xtal1 14 17 xtal2 11 12, 13 v dd 31 24, 37, 38 v ss 25 29 pref1/p30 48 nc 6nc table 5. 40- and 48-pin configuration (continued) 40-pin pdip # 48-pin ssop # symbol
zgp323h product specification ps023806-0506 pin description 10 pin functions xtal1 crystal 1 (time-based input) this pin connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator input. additionally, an optional external single-phase cl ock can be coded to the on-chip oscillator input. xtal2 crystal 2 (time-based output) this pin connects a parallel-resonant crystal or ceramic resonant to the on-chip oscillator output. input/output ports input/output ports are describe d in the following sections. the cmos input buffer for each port 0, 1, or 2 pin is always connected to the pin, even when the pin is configured as an output. if th e pin is configured as an open-drain output and no signal is applied, a high output st ate can cause the cmos input buffer to float. this might lead to excessive le akage current of more than 100 a. to prevent this leak- age, connect the pin to an external signal with a defined logic level or or insure its output state is low, especially during stop mode. internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode. port 0, 1 and 2 have both input and output capability. the input logic is always present no matter whether the port is configured as input or output. when doing a read in- struction, it will read the actual value at th e input logic not from the output buffer. in addition, the instruction of "or", "and", " xor" are read-modify-write instructions. it will first read the port and then modify the value and load back to the port. precaution should be taken if the port is co nfigured as open-drain output or driving some circuit that may make the voltage different from the desired output logic. for example, pins p00-p07 are not connecting to anything el se. if it is configured as open-drain output 14 nc 30 nc 36 nc table 5. 40- and 48-pin configuration (continued) 40-pin pdip # 48-pin ssop # symbol caution:
zgp323h product specification ps023806-0506 pin description 11 with outputting logic one, it is a floating po rt and will read back as zero. the follow- ing instruction will set p00-p07 all low. and p0,#%f0 port 0 (p07?p00) port 0 is an 8-bit, bidirectional, cmos-com patible port. these eight i/o lines are config- ured under software control as a nibble i/o po rt. the output drivers are push-pull or open- drain controlled by bit d2 in the pcon register. if one or both nibbles are needed for i/o operation, they must be configured by writing to the port 0 mode register. after a hardware re set, port 0 is configured as an input port. an optional pull-up transistor is available as a mask option on all port 0 bits with nibble select. internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode. the port 0 direction is reset to its default state following an smr. notes:
zgp323h product specification ps023806-0506 pin description 12 figure 7. port 0 configuration port 1 (p17?p10) port 1 (see figure 8 ) port 1 can be configured for standard port input or output mode. after por, port 1 is configured as an input po rt. the output drivers ar e either push-pull or open-drain and are controlled by bit d1 in the pcon register. the port 1 direction is reset to its default state following an smr. otp programming option 4 4 z8 gp otp port 0 (i/o) pad in out i/o open-drain resistive transistor pull-up v cc note:
zgp323h product specification ps023806-0506 pin description 13 figure 8. port 1 configuration port 2 (p27?p20) port 2 is an 8-bit, bidirectiona l, cmos-compatible i/o port (see figure 9 ). these eight i/o lines can be independently configured under so ftware control as inputs or outputs. port 2 is always available for i/o operation. a mask option is available to connect eight pull-up transistors on this port. bits programmed as outputs are globally programmed as either push-pull or open-drain. the po r resets with the eight bits of port 2 configured as inputs. port 2 also has an 8-bit input or and and ga te, which can be used to wake up the part. p20 can be programmed to access the edge -detection circuitry in demodulation mode. otp programming option 8 z8 gp otp port 1 (i/o) pad in out oen open-drain resistive transistor pull-up v cc
zgp323h product specification ps023806-0506 pin description 14 figure 9. port 2 configuration port 3 (p37?p30) port 3 is a 8-bit, cmos-compatible fixed i/o port (see figure 10 ). port 3 consists of four fixed input (p33?p30) and four fixed output (p37?p34), which can be configured under software control for interrupt and as output from the counter/timers. p30, p31, p32, and p33 are standard cmos inputs; p34, p35, p36, and p37 are push-pull outputs. otp programming option z8 gp otp port 2 (i/o) pad in out i/o open-drain resistive transistor pull-up v cc
zgp323h product specification ps023806-0506 pin description 15 figure 10. port 3 configuration two on-board comparators process analog signal s on p31 and p32, with reference to the voltage on pref1 and p33. the analog function is enabled by programming the port 3 mode register (bit 1). p31 and p32 are programm able as rising, falling, or both edge trig- gered interrupts (irq register bits 6 and 7). pref1 and p33 are the comparator reference voltage inputs. access to the counter timer edge-detection circuit is through p31 or p20 (see ?t8 and t16 common functions?ctr1(0d)01h? on page 29). other edge detect and irq modes are described in table 6 . - z8 gp otp port 3 (i/o) p32 (an2) p31 (an1) pref1 from stop mode recovery source of smr p33 (ref2) irq2, p31 data pref1/p30 p31 p32 p33 p34 p35 p36 p37 d1 1 = analog 0 = digital r247 = p3m + - + irq0, p32 data irq1, p33 data comp 1 comp2 dig. an.
zgp323h product specification ps023806-0506 pin description 16 comparators are powered down by entering stop mode. for p31?p33 to be used in a stop mode recovery (smr) source, these inpu ts must be placed into digital mode. 2 port 3 also provides output for each of the counter/timers and the and/or logic (see figure 11 ). control is performed by programmin g bits d5?d4 of ctr1, bit 0 of ctr0, and bit 0 of ctr2. table 6. port 3 pin function summary pin i/o counter/timers comparator interrupt pref1/p30 in rf1 p31 in in an1 irq2 p32 in an2 irq0 p33 in rf2 irq1 p34 out t8 ao1 p35 out t16 p36 out t8/16 p37 out ao2 p20 i/o in note:
zgp323h product specification ps023806-0506 pin description 17 figure 11. port 3 counter/timer output configuration pad p34 comp 1 v dd mux pcon, d0 mu x ctr0, d0 p31 p30 (pref 1) p34 data t8_out + pad p35 v dd mux ctr2, out 35 t16_out pad p36 v dd mux ctr1, d6 out 36 t8/ pad p3 v dd mux pcon, d0 p37 data - p31 p3m d1 comp 2 p32 p33 + - p32 p3m d1
zgp323h product specification ps023806-0506 pin description 18 comparator inputs in analog mode, p31 and p32 have a comparat or front end. the comparator reference is supplied to p33 and pref1. in this mode, the p33 internal data latch and its corresponding irq1 are diverted to the smr sources (exclu ding p31, p32, and p33) as indicated in figure 10 on page 15. in digital mode, p33 is used as d3 of the port 3 input register, which then generates irq1. comparators are powered down by entering stop mode. for p31?p33 to be used in a stop mode recovery source, these inputs must be placed into digital mode. comparator outputs these channels can be programmed to be output on p34 and p37 through the pcon regis- ter. reset (input, active low) reset initializes the mcu and is accomplis hed either through power-on, watch-dog timer, stop mode recovery, low-voltage detec tion, or external rese t. during power-on reset and watch-dog timer reset, the interna lly generated reset drives the reset pin low for the por time. any devices driving the extern al reset line must be open-drain to avoid damage from a possible conflict during reset conditions. pull-up is provided internally. when the z8 gp asserts (low) the reset pin, the internal pull-up is disabled. the z8 gp does not assert the reset pin when under vbo. the external reset does not in itiate an exit from stop mode. note: note:
zgp323h product specification ps023806-0506 functional description 19 functional description this device incorporates special functions to enhance the z8 ? functionality in consumer and battery-operated applications. program memory this device addresses up to 32 kb of otp memory. the first 12 bytes are reserved for interrupt vectors. these locations contain the six 16-bit vectors that correspond to the six available interrupts. ram this device features 256 b of ram. see figure 12 .
zgp323h product specification ps023806-0506 functional description 20 figure 12. program me mory map (32 k otp) expanded register file the register file has been expa nded to allow for additional sy stem control registers and for mapping of additional peripheral devices into the register address area. the z8 ? register address space (r0 through r15) has been implemented as 16 ba nks, with 16 registers per bank. these register groups are known as the erf (expanded register file). bits 7?4 of on-chip rom reset start irq5 irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 12 11 10 9 8 7 6 5 4 3 2 1 0 32768 location of first byte of instruction executed after reset interrupt vector (lower interrupt vector (upper not accessible
zgp323h product specification ps023806-0506 functional description 21 register rp select the working register group. bits 3?0 of register rp select the expanded register file bank. an expanded register bank is also referred to as an expanded register group (see figure 13 ). note:
zgp323h product specification ps023806-0506 functional description 22 figure 13. expanded register file architecture uuuuuuu0 00000000 00000000 00000000 00 0f 7f f0 ff ff spl 00000000 uuuuuuuu 00000000 uuuuuuuu uuuuuuuu uuuuuuuu 11111111 00000000 11001111 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu fe sph fd rp fc flags fb imr fa irq f9 ipr f8 p01m f7 p3m f6 p2m f5 reserved f4 reserved f3 reserved f2 reserved f1 reserved f0 reserved d7 d6 d5 d4 d3 d2 d1 d0 uu001101 u01000u0 11111110 (f) 0f wdtmr (f) 0e reserved (f) 0d smr2 (f) 0c reserved (f) 0b smr (f) 0a reserved (f) 09 reserved (f) 08 reserved (f) 07 reserved (f) 06 reserved (f) 05 reserved (f) 04 reserved (f) 03 reserved (f) 02 reserved (f) 01 reserved (f) 00 pcon 76543210 expanded register bank pointer working register uuuuuuuu uuuuuuuu 00000000 (d) 0c lvd (d) 0b hi8 (d) 0a lo8 (d) 09 hi16 (d) 08 lo16 (d) 07 tc16h (d) 06 tc16l (d) 05 tc8h (d) 04 tc8l (d) 03 ctr3 (d) 02 ctr2 (d) 01 ctr1 (d) 00 ctr0 group pointer register file (bank 0)** 00011111 * * 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 u = unknown * is not reset with a stop-mode recovery ** all addresses are in hexadecimal is not reset with a stop-mode recovery, except bit 0 bit 5 is not reset with a stop-mode recovery bits 5,4,3,2 not reset with a stop-mode recovery bits 5 and 4 not reset with a stop-mode recovery bits 5,4,3,2,1 not reset with a stop-mode recovery expanded reg. bank 0/group (0) * (0) 03 p3 (0) 02 p2 (0) 01 p1 (0) 00 p0 0 u u u u * * * * * * * * * * * expanded reg. bank f/group 0** expanded reg. bank 0/group 15** register pointer z8 ? standard control registers expanded reg. bank d/group 0 r ese t c on diti on
zgp323h product specification ps023806-0506 functional description 23 the upper nibble of the register pointer (see figure 14 ) selects which working register group, of 16 bytes in the register file, is accessed out of the possible 256. the lower nibble selects the expanded register file bank and, in the case of the z8 gp family, banks 0, f, and d are implemented. a 0h in the lower nibble allows the norm al register file (bank 0) to be addressed. any other value from 1h to fh exchanges the lower 16 registers to an expanded register bank. figure 14. register pointer example: z8 gp: (see figure 13 on page 22) r253 rp = 00h r0 = port 0 r1 = port 1 r2 = port 2 r3 = port 3 but if: r253 rp = 0dh r0 = ctr0 r1 = ctr1 r2 = ctr2 r3 = reserved the counter/timers are mapped into erf grou p d. access is easily performed using the following: ld rp, #0dh ; select erf d for access to bank d ; (working register group 0) ld r0,#xx ; load ctr0 ld 1, #xx ; load ctr1 r253 rp d7 d6 d5 d4 d3 d2 d1 d0 expanded register file pointer working register pointer default setting after reset = 0000 0000
zgp323h product specification ps023806-0506 functional description 24 ld r1, 2 ; ctr2 ctr1 ld rp, #0dh ; select erf d for access to bank d ; (working register group 0) ld rp, #7dh ; select expanded register bank d and working ; register group 7 of bank 0 for access. ld 71h, 2 ; ctrl2 register 71h ld r1, 2 ; ctrl2 register 71h register file the register file (bank 0) consists of 4 i/o por t registers, 237 general-purpose registers, 16 control and status registers (r0?r3, r4?r239, and r240?r255, respectively), and two expanded registers groups in banks d (see table 7 ) and f. instructions can access registers directly or indirectly through an 8-bit address field, thereby allowing a short, 4-bit register address to use the register pointer ( figure 15 ). in the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. the register pointer addresses the starting locatio n of the active working register group. working register group e0?ef can only be accessed through working registers and indi- rect addressing modes. note:
zgp323h product specification ps023806-0506 functional description 25 figure 15. register pointer?detail stack the internal register file is used for the st ack. an 8-bit stack pointer spl (r255) is used for the internal stack that resides in the ge neral-purpose registers (r4?r239). sph (r254) can be used as a general-purpose register. r 7 r 6 r 5 r 4 r 3 r 2 r 1 r the upper nibble of the register file address provided by the register pointer specifies the active working-register group. specified working register group register group 1 register group 0 i/o ports r253 the lower nibble of the register file address provided by the instruction points to the specified register. * rp = 00: selects register bank 0, working register group 0 r15 to r0 r15 to r4 * r3 to r0 * ff f0 ef e0 df d0 40 3f 30 2f 20 1f 10 0f 00 register group 2
zgp323h product specification ps023806-0506 functional description 26 timers t8_capture_hi?hi8(d)0bh this register holds the captured data from th e output of the 8-bit counter/timer0. typi- cally, this register holds the number of counts when the input signal is 1. t8_capture_lo?l08(d)0ah this register holds the captured data from th e output of the 8-bit counter/timer0. typi- cally, this register holds the number of counts when the input signal is 0. t16_capture_hi?hi16(d)09h this register holds the captured data from th e output of the 16-bit counter/timer16. this register holds the ms-byte of the data. t16_capture_lo?l016(d)08h this register holds the captured data from th e output of the 16-bit counter/timer16. this register holds the ls-byte of the data. counter/timer2 ms-byte hold register?tc16h(d)07h field bit position description t8_capture_hi [7:0] r/w captured data - no effect field bit position description t8_capture_l0 [7:0] r/w captured data - no effect field bit position description t16_capture_hi [7:0] r/w captured data - no effect field bit position description t16_capture_l o [7:0] r/w captured data - no effect field bit position description t16_data_hi [7:0] r/w data
zgp323h product specification ps023806-0506 functional description 27 counter/timer2 ls-byte hold register?tc16l(d)06h counter/timer8 high hold register?tc8h(d)05h counter/timer8 low hold register?tc8l(d)04h ctr0 counter/timer8 control register?ctr0(d)00h table 7 lists and briefly describes the fields for this register. field bit position description t16_data_lo [7:0] r/w data field bit position description t8_level_hi [7:0] r/w data field bit position description t8_level_lo [7:0] r/w data table 7. ctr0(d)00h counter/timer8 control register field bit position value description t8_enable 7------- r/w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------- r/w 0* 1 modulo-n single pass time_out --5------ r/w 0** 1 0 1 no counter time-out counter time-out occurred no effect reset flag to 0 t8 _clock ---43--- r/w 0 0** 0 1 1 0 1 1 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0** 1 disable data capture interrupt enable data capture interrupt
zgp323h product specification ps023806-0506 functional description 28 t8 enable this field enables t8 when set (written) to 1. single/modulo-n when set to 0 (modulo-n), the counter reloads the in itial value when the terminal count is reached. when set to 1 (single-pass), the coun ter stops when the terminal count is reached. timeout this bit is set when t8 times ou t (terminal count reached). to r eset this bit, write a 1 to its location. writing a 1 is the only way to reset the termin al count status condition. reset this bit before using/enablin g the counter/timers. the first clock of t8 might not have complete clock width and can occur any time when enabled. take care when using the or or and comman ds to manipulate ct r0, bit 5 and ctr1, bits 0 and 1 (demodulation mode). these in structions use a read-modify-write sequence in which the current status from the ctr0 an d ctr1 registers is ored or anded with the designated value and then writ ten back into the registers. t8 clock this bit defines the frequency of the input signal to t8. capture_int_mask set this bit to allow an interrupt when data is captured into either lo8 or hi8 upon a posi- tive or negative edge detection in demodulation mode. counter_int_mask ------1- r/w 0** 1 disable time-out interrupt enable time-out interrupt p34_out -------0 r/w 0* 1 p34 as port output t8 output on p34 note: * indicates the value upon power-on reset. * *indicates the value upon power-on reset. not reset with a stop mode recovery. table 7. ctr0(d)00h counter/timer8 control register (continued) field bit position value description caution: note:
zgp323h product specification ps023806-0506 functional description 29 counter_int_mask set this bit to allow an interrupt when t8 has a timeout. p34_out this bit defines whether p34 is used as a normal output pin or the t8 output. t8 and t16 common functions?ctr1(0d)01h this register controls the functions in common with the t8 and t16. table 8 lists and briefly describes the fields for this register. table 8. ctr1(0d)01h t8 and t16 common functions field bit position value description mode 7------- r/w 0* transmit mode demodulation mode p36_out/ demodulator_input -6------ r/w 0* 1 0* 1 transmit mode port output t8/t16 output demodulation mode p31 p20 t8/t16_logic/ edge _detect --54---- r/w 00** 01 10 11 00** 01 10 11 transmit mode and or nor nand demodulation mode falling edge rising edge both edges reserved transmit_submode/ glitch_filter ----32-- r/w 00* 01 10 11 00* 01 10 11 transmit mode normal operation ping-pong mode t16_out = 0 t16_out = 1 demodulation mode no filter 4 sclk cycle 8 sclk cycle reserved
zgp323h product specification ps023806-0506 functional description 30 mode if the result is 0, the counter/timers are in transmit mode; otherwise, they are in demodulation mode. p36_out/demodulator_input in transmit mode, this bit defines whether p36 is used as a normal output pin or the combined output of t8 and t16. in demodulation mode, this bit defines whet her the input signal to the counter/tim- ers is from p20 or p31. if the input signal is from port 31, a capture ev ent may also generate an irq2 interrupt. to prevent generating an irq2, e ither disable the irq2 interru pt by clearing its imr bit d2 or use p20 as the input. t8/t16_logic/edge _detect in transmit mode, this field defines how the outputs of t8 and t16 are combined (and, or, nor, nand). in demodulation mode, this field defines whic h edge should be detected by the edge detector. transmit_submode/glitch filter initial_t8_out/ rising edge ------1- r/w r w 0* 1 0* 1 0 1 transmit mode t8_out is 0 initially t8_out is 1 initially demodulation mode no rising edge rising edge detected no effect reset flag to 0 initial_t16_out/ falling_edge -------0 r/w r w 0* 1 0* 1 0 1 transmit mode t16_out is 0 initially t16_out is 1 initially demodulation mode no falling edge falling edge detected no effect reset flag to 0 note: *default at power-on reset * default at power-on reset. not reset with stop mode recovery. table 8. ctr1(0d)01h t8 and t16 common functions (continued) field bit position value description
zgp323h product specification ps023806-0506 functional description 31 in transmit mode, this field defines whether t8 and t16 are in the ping-pong mode or in independent normal operation mode. se tting this field to ?normal operation mode? terminates the ?ping-pong mode? oper ation. when set to 10, t16 is immedi- ately forced to a 0; a setting of 11 forces t16 to output a 1. in demodulation mode, this field defines th e width of the glitch th at must be filtered out. initial_t8_out/rising_edge in transmit mode, if 0, the outp ut of t8 is set to 0 when it starts to count. if 1, the out- put of t8 is set to 1 when it st arts to count. when the counter is not enab led and this bit is set to 1 or 0, t8_out is set to the opposite state of this bit. this ensures that when the clock is enabled, a transition occurs to the initial state set by ctr1, d1. in demodulation mode, this bit is set to 1 wh en a rising edge is detected in the input signal. in order to reset the mode, a 1 should be written to this location. initial_t16 out/falling _edge in transmit mode, if it is 0, the output of t16 is set to 0 when it starts to count. if it is 1, the output of t16 is set to 1 when it starts to count. this bit is effective only in normal or ping-pong mode (ctr1, d3 ; d2). when the counter is not enabled and this bit is set, t16_out is set to th e opposite state of this bit. this ensures that when the clock is enabled, a transition occurs to the initial state set by ctr1, d0. in demodulation mode, this b it is set to 1 when a falling ed ge is detected in the input signal. in order to reset it, a 1 should be written to this location. modifying ctr1 (d1 or d0) while the coun ters are enabled causes unpredictable output from t8/16_out. ctr2 counter/timer 16 control register?ctr2(d)02h table 9 lists and briefly describes the fields for this register. note:
zgp323h product specification ps023806-0506 functional description 32 t16_enable this field enables t16 when set to 1. single/modulo-n in transmit mode, when set to 0, the coun ter reloads the initial value when it reaches the terminal count. when set to 1, the counter stops wh en the terminal count is reached. table 9. ctr2(d)02h: counter/timer16 control register field bit position value description t16_enable 7------- r w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------ r/w 0* 1 0 1 transmit mode modulo-n single pass demodulation mode t16 recognizes edge t16 does not recognize edge time_out --5----- r w 0* 1 0 1 no counter timeout counter timeout occurred no effect reset flag to 0 t16 _clock ---43--- r/w 00** 01 10 11 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0** 1 disable data capture int. enable data capture int. counter_int_mask ------1- r/w 0* disable timeout int. enable timeout int. p35_out -------0 r/w 0* 1 p35 as port output t16 output on p35 note: *indicates the value upon power-on reset. ** indicates the value upon power-on reset. not reset with a stop mode recovery.
zgp323h product specification ps023806-0506 functional description 33 in demodulation mode, when set to 0, t16 captures and relo ads on detection of all the edges. when set to 1, t16 capt ures and detects on the first ed ge but ignores the subsequent edges. for details, see the description of t16 demodulation mode on page 41. time_out this bit is set when t16 times out (terminal count reached). to reset the bit, write a 1 to this location. t16_clock this bit defines the frequency of th e input signal to counter/timer16. capture_int_mask this bit is set to allow an interrupt when data is cap tured into lo16 and hi16. counter_int_mask set this bit to allow an interrupt when t16 times out. p35_out this bit defines whether p35 is used as a normal output pin or t16 output. ctr3 t8/t16 control register?ctr3(d)03h table 10 lists and briefly describes the fields for th is register. this register allows the t 8 and t 16 counters to be synchronized. table 10. ctr3 (d)03h: t8/t16 control register field bit position value description t 16 enable 7------- r r w w 0* 1 0 1 counter disabled counter enabled stop counter enable counter t 8 enable -6------ r r w w 0* 1 0 1 counter disabled counter enabled stop counter enable counter sync mode --5----- r/w 0** 1 disable sync mode enable sync mode
zgp323h product specification ps023806-0506 functional description 34 counter/timer functional blocks input circuit the edge detector monitors the input signal on p31 or p20. based on ctr1 d5?d4, a pulse is generated at the pos edge or neg edge line when an edge is detected. glitches in the input signal that have a width less than specified (ctr1 d3, d2) are filtered out (see figure 16 ). figure 16. glitch filter circuitry t8 transmit mode before t8 is enabled, the output of t8 depend s on ctr1, d1. if it is 0, t8_out is 1; if it is 1, t8_out is 0. see figure 17 . reserved ---43210 r w 1 x always reads 11111 no effect *indicates the value upon power-on reset. ** indicates the value upon power-on reset. not reset with a stop mode recovery. table 10. ctr3 (d)03h: t8/t16 control register (continued) field bit position value description mux glitch filter edge detector p31 p20 pos edge neg edge ctr1 d5,d4 ctr1 d6 ctr1 d3, d2
zgp323h product specification ps023806-0506 functional description 35 figure 17. transmit mode flowchart set timeout status bit (ctr0 d5) and generate timeout_int if enabled set timeout status bit (ctr0 d5) and generate timeout_int if enabled t8 (8-bit) transmit mode no t8_enable bit set ctr0, d7 yes ctr1, d1 value reset t8_enable bit 0 1 load tc8l reset t8_out load tc8h set t8_out enable t8 no t8_timeout yes single pass single modulo-n t8_out value 0 enable t8 no t8_timeout ye s pass? load tc8h set t8_out load tc8l reset t8_out 1
zgp323h product specification ps023806-0506 functional description 36 when t8 is enabled, the outp ut t8_out switches to the initial value (ctr1, d1). if the initial value (ctr1, d1) is 0, tc8l is loaded; otherwise, tc8h is loaded into the counter. in single-pass mode (ctr0, d6), t8 counts down to 0 and stops, t8_out toggles, the timeout status bit (ctr0, d5) is set, and a timeout interrupt can be generated if it is enabled (ctr0, d1). in modulo-n mode, upon reaching terminal co unt, t8_out is tog- gled, but no interrupt is generated. from that point, t8 loads a ne w count (if the t8_out level now is 0), tc8l is loaded; if it is 1, tc 8h is loaded. t8 counts down to 0, toggles t8_out, and sets the timeout status bit (ctr 0, d5), thereby generating an interrupt if enabled (ctr0, d1). one cycle is thus comp leted. t8 then loads from tc8h or tc8l according to the t8_out level and repeats the cycle. see figure 18 . figure 18. 8-bit counter/timer circuits you can modify the values in tc8h or tc8l at any time. the new values take effect when they are loaded. to ensure known operation do not write thes e registers at the time the values are to be loaded into the counter/timer. an initial count of 1 is not allowed (a non-function oc- curs). an initial count of 0 cau ses tc8 to count from 0 to ffh to feh . the letter h denotes hexadecimal values. transition from 0 to ffh is not a timeout condition. ctr0 d1 negative edge positive edge z8 ? data bus irq4 ctr0 d2 sclk z8 ? data bus ctr0 d4, clock t8_out lo8 tc8h tc8l clock select 8-bit counter t8 hi8 caution: note:
zgp323h product specification ps023806-0506 functional description 37 using the same instructions fo r stopping the counter/timers and setting the status bits is not recommended. two successive commands are necessary. first, the counte r/timers must be stopped. sec- ond, the status bits must be reset. these commands are required because it takes one counter/timer clock interval for the in itiated event to actually occur. see figure 19 and figure 20 . figure 19. t8_out in single-pass mode figure 20. t8_out in modulo-n mode t8 demodulation mode the user must program tc8l and tc8h to ffh . after t8 is enabled, when the first edge (rising, falling, or both depending on ctr1, d5; d4) is detected, it starts to count down. when a subsequent edge (rising , falling, or both depending on ctr1, d5; d4) is detected during counting, the current value of t8 is complemented and put in to one of the capture registers. if it is a positive edge, data is put in to lo8; if it is a negative edge, data is put into hi8. from that point, one of the edge dete ct status bits (ctr1, d1; d0) is set, and an interrupt can be generated if enabled (ctr 0, d2). meanwhile, t8 is loaded with ffh and starts counting again. if t8 reaches 0, the tim eout status bit (ctr0, d5) is set, and an caution: tc8h counts counter enable command; t8_out switches to its initial value (ctr1 d1) t8_out toggles; timeout interrupt counter enable command; t8_out switches to its timeout interrupt timeout interrupt t8_out t8_out toggles tc8l tc8 tc8 tc8l tc8l ...
zgp323h product specification ps023806-0506 functional description 38 interrupt can be generated if enabled (ctr 0, d1). t8 then continues counting from ffh (see figure 21 and figure 22 ). figure 21. demodulation mode count capture flowchart t8 (8-bit) count capture t8 enable (set by user) no yes edge present what kind of edge t8 hi8 no yes negative ffh t8 positive t8 lo8
zgp323h product specification ps023806-0506 functional description 39 figure 22. demodulation mode flowchart t8 (8-bit) demodulation mode t8 enable ctr0, d7 no yes ffh tc8 first edge present enable tc8 t8_enable bit set edge present t8 timeout set edge present status bit and trigger data capture int. if enabled set timeout status bit and trigger timeout int. if enabled continue counting disable tc8 no yes no yes yes yes no no
zgp323h product specification ps023806-0506 functional description 40 t16 transmit mode in normal or ping-pong mode, the output of t16 when not enabled, is dependent on ctr1, d0. if it is a 0, t16_out is a 1; if it is a 1, t16_out is 0. you can force the output of t16 to either a 0 or 1 whether it is enable d or not by programming ctr1 d3; d2 to a 10 or 11. when t16 is enabled, tc16h * 256 + tc16l is loaded, and t16_out is switched to its initial value (ctr1, d0). when t16 counts down to 0, t16_out is toggled (in nor- mal or ping-pong mode), an interrupt (ctr2, d1) is generated (if enabled), and a sta- tus bit (ctr2, d5) is set. see figure 23 . figure 23. 16-bit counter/timer circuits global interrupts override this function as described in ?interrupts? on page 44. if t16 is in single-pass mode, it is stopped at this point (see figure 24 ). if it is in mod- ulo-n mode, it is loaded with tc16h * 256 + tc16l, and the counting continues (see figure 25 ). you can modify the values in tc16h and tc16 l at any time. the new values take effect when they are loaded. ctr2 d1 negative edge positive edge z8 ? data bus irq3 ctr2 d2 sclk z8 ? data bus ctr2 d4, clock t16_out lo16 tc16 tc16 clock select 16-bit counter t16 hi16 note:
zgp323h product specification ps023806-0506 functional description 41 do not load these registers at the time the va lues are to be loaded into the counter/timer to ensure known operation. an initial count of 1 is not a llowed. an initial count of 0 causes t16 to count from 0 to ffffh to fffeh . transition from 0 to ffffh is not a tim- eout condition. figure 24. t16_out in single-pass mode figure 25. t16_out in modulo-n mode t16 demodulation mode the user must program tc16l and tc16h to ffh . after t16 is enabled, and the first edge (rising, falling, or both depending on ctr1 d5; d4) is detected, t16 captures hi16 and lo16, reloads, and begins counting. if d6 of ctr2 is 0 when a subsequent edge (rising , falling, or both depending on ctr1, d5; d4) is detected during counting, the current count in t16 is complemented and put into hi16 and lo16. when data is captured, one of the edge detect status bits (ctr1, d1; d0) is set, and an interrupt is generated if enabled (ctr2, d2). t16 is loaded with ffffh and starts again. this t16 mode is generally used to measure space time, the length of time between bursts of carrier signal (marks). if d6 of ctr2 is 1 caution: tc16h*256+tc16l counts ?counter enable? command t16_out switches to its initial value (ctr1 d0) t16_out toggles, timeout interrupt tc16h*256+tc16l tc16h*256+tc16 tc16h*256+tc16 t16_out toggles, timeout interrupt t16_out toggles, timeout interrupt ?counter enable? command, t16_out switches to its initial value (ctr1 d0) tc16_out ...
zgp323h product specification ps023806-0506 functional description 42 t16 ignores the subsequent edges in the inpu t signal and continues counting down. a tim- eout of t8 causes t16 to capture its current value and generate an interrupt if enabled (ctr2, d2). in this case, t16 does not relo ad and continues counting. if the d6 bit of ctr2 is toggled (by writing a 0 then a 1 to it) , t16 captures and reload s on the next edge (rising, falling, or both depending on ctr1, d5 ; d4), continuing to ignore subsequent edges. this t16 mode generally measur es mark time, the length of an active carrier signal burst. if t16 reaches 0, t16 continues counting from ffffh . meanwhile, a status bit (ctr2 d5) is set, and an interrupt timeout can be generated if enabled (ctr2 d1). ping-pong mode this operation mode is only valid in trans mit mode. t8 and t16 must be programmed in single-pass mode (ctr0, d6; ctr2, d6), and ping-pong mode must be programmed in ctr1, d3; d2. the user can begin the operation by enabling either t8 or t16 (ctr0, d7 or ctr2, d7). for example, if t8 is en abled, t8_out is set to this initial value (ctr1, d1). according to t8_o ut's level, tc8h or tc8l is loaded into t8. after the terminal count is reached, t8 is disabled, and t16 is enable d. t16_out then switches to its initial value (ctr1, d0), data from tc16h and tc16l is loaded, and t16 starts to count. after t16 reaches the terminal count, it stops, t8 is enabled again, repeating the entire cycle. interrupts can be allowed when t8 or t16 reaches terminal control (ctr0, d1; ctr2, d1). to stop the ping-pong operation, write 00 to bits d3 and d2 of ctr1. see figure 26 . enabling ping-pong operation while the counter /timers are running might cause intermit- tent counter/timer function. disable the count er/timers and reset the status flags before instituting this operation. figure 26. ping-pong mode diagram initiating ping-pong mode note: enabl tc8 enable timeout tc16 ping-pong ctr1 timeout
zgp323h product specification ps023806-0506 functional description 43 first, make sure both counter/timers are no t running. set t8 into single-pass mode (ctr0, d6), set t16 into single-pass mode (ctr2, d6), and set the ping-pong mode (ctr1, d2; d3). these instructions can be in random order. finally, start ping-pong mode by enabling either t8 (ctr0, d7) or t16 (ctr2, d7). see figure 27 . figure 27. output circuit the initial value of t8 or t16 must not be 1 . stopping the timer and restarting the timer reloads the initial value to avoi d an unknown pr evious value. t16_out mux ctr1 d3 t8_out p34 and/or/nor/ nand mux mux mux p35 p36 p34_internal ctr1 d5, d4 p36_internal p35_internal ctr1, ctr0 d0 ctr1 d6 ctr2 d0
zgp323h product specification ps023806-0506 functional description 44 during ping-pong mode the enable bits of t8 and t16 (ctr0, d7; ctr2, d7) are set and cleared alternately by hardware. the timeout bits (ctr0, d5; ctr2 , d5) are set every time the counter/timers reach the terminal count. interrupts the zgp323h features six different interrupts ( table 11 ). the interrupts are maskable and prioritized ( figure 28 ). the six sources are divided as follows: three sources are claimed by port 3 lines p33?p31, two by the counter/timers ( table 11 ) and one for low voltage detection. the interrupt mask register (globa lly or individually) enables or disables the six interrupt requests. the source for irq is determined by bit 1 of th e port 3 mode register (p3m). when in dig- ital mode, pin p33 is the source. when in anal og mode the output of the stop mode recov- ery source logic is used as the source for the interrupt. see figure 33 , stop mode recovery source, on page 53.
zgp323h product specification ps023806-0506 functional description 45 figure 28. interrupt block diagram low- voltage timer 8 timer 16 interrupt edge imr ipr priority logic irq 5 irq2 irq irq irq3 irq4 irq5 p31 p32 irq register d6, d7 global interrupt enable interrupt request vector select d1 of p3m register p33 0 1 stop mode recovery source
zgp323h product specification ps023806-0506 functional description 46 when more than one interrupt is pending, pr iorities are resolved by a programmable prior- ity encoder controlled by the interrupt priority register. an interrupt machine cycle acti- vates when an interrupt request is granted. as a result, all subsequent interrupts are disabled, and the program counter and status flags are saved. the cy cle then branches to the program memory vector lo cation reserved for that inte rrupt. all zgp323h interrupts are vectored through locations in the program memory. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommodate polle d interrupt systems, interrupt inputs are masked, and the interrupt request register is polled to dete rmine which of the interrupt requests require service. an interrupt resulting from an 1 is mapped into irq2, an d an interrupt from an2 is mapped into irq0. interrupts ir q2 and irq0 can be rising, falling, or both edge trig- gered. these interrupts are programmable by th e user. the software ca n poll to identify the state of the pin. programming bits for the interru pt edge select are located in the irq register (r250), bits d7 and d6. the config uration is indicated in table 12 . table 11. interrupt types, sources, and vectors name source vector location comments irq0 p32 0,1 external (p32), ri sing, falling edge triggered irq1 p33 2,3 external (p33), falling edge triggered irq2 p31, t in 4,5 external (p31), rising, falling edge triggered irq3 t16 6,7 internal irq4 t8 8,9 internal irq5 lvd 10,11 internal table 12. irq register irq interrupt edge d7 d6 irq2 (p31) irq0 (p32) 00f f 01f r 10r f 11r/f r/f note: f = falling edge; r = rising edge
zgp323h product specification ps023806-0506 functional description 47 clock the device?s on-chip oscillator has a high-gain, parallel-resonant ampl ifier, for connection to a crystal or ceramic resonator, or any su itable external clock source (xtal1 = input, xtal2 = output). the crystal must be at cu t, 1 mhz to 8 mhz maximum, with a series resistance (rs) less than or equal to 100 . the on-chip oscillator can be driven with a suitable external clock source. the crystal must be connected across xt al1 and xtal2 using the recommended capac- itors from each pin to ground. the typical capac itor value is 10 pf for 8 mhz. please also check with the crystal supplie r for the optimum capacitance. figure 29. oscillator configuration the zilog?s zgp323h supports crystal, resonato r, and oscillator. most resonators have a frequency tolerance of less than +/-0.5% wh ich is adequate for remote control applica- tions. the typical resonator has a very fast start up time on the order of a few hundred microseconds. most crystals have a frequency tolerance of l ess than 50 ppm (+/-0.005%). crystal oscilla- tors, however, require a much longer start- up time because the large loading capacitance slows down oscillation start-up. zilog recomm ends using loading capa citors of no more than 10pf for crystal oscillators. if the stray ca pacitance of the pcb or the crystal is high, the loading capacitance c1 and c2 should be further reduced to ensure stable oscillation before t por . (power on reset time is typically 5-6ms. refer to table 23, ?ac charac- teristics,? on page 81, for more information.) for stop mode recovery operation, bit 5 of th e smr register allows user to select the stop mode recovery delay (t por ). if it is not selected, the mcu will execute instruction c1 c2 xtal xtal xtal xtal crystal c1, c2 = 10pf typ * f = 8mhz * preliminary value in cluding pin parasitics external clock xtal xtal ceramic resonator f = 8mhz
zgp323h product specification ps023806-0506 functional description 48 immediately after it wakes up from stop mode. the stop mode recovery delay must be selected (bit 5 of smr = 1) if resonator or crystal is used as clock source. for both resonator and crystal oscillation, the oscillation grou nd must go directly to the ground pin of the microcontroller. it should use the shortest distant and isolate from other connection. power-on reset a timer circuit clocked by a dedicated on-boar d rc-oscillator is used for the power-on reset (por) timer function. the por time allows v dd and the oscillator circuit to stabi- lize before instruction execution begins. the por timer circuit is a one-shot time r triggered by one of three conditions: ? power fail to power ok status, including waking up from v bo standby ? stop-mode recovery (if d5 of smr = 1) ? wdt timeout the por timer is 2.5 ms minimum. bit 5 of the stop-mode register determines whether the por timer is bypassed after stop-mode recovery (typical for external clock). halt mode this instruction turns off the internal cpu clock, but not the xt al oscillation. the counter/timers and external interrupts irq0, irq1, irq2, irq3, irq4, and irq5 remain active. the devices are recovered by interrupts, either externally or internally generated. an interrupt request must be executed (enabl ed) to exit halt mode. after the interrupt service routine, the program continues from the instructi on after halt mode. stop mode this instruction turns off the internal clock and external cr ystal oscillation, reducing the standby current to 10 a or less. stop mode is terminated only by a reset, such as wdt timeout, por, smr or external reset. this condition causes the processor to restart the application program at address 000ch . to enter stop (or halt) mode, first flush the instruction pipeline to avoid suspending execution in mid- instruction. execute a nop (opcode = ffh ) immediately before the appropria te sleep instruction, as follows:
zgp323h product specification ps023806-0506 functional description 49 ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode port configuration register the port configuration (pcon) register ( figure 30 ) configures the comparator output on port 3. it is located in the expand ed register 2 at bank f, location 00. pcon(fh)00h figure 30. port configuration re gister (pcon) (write only) comparator output port 3 (d0) bit 0 controls the comparator used in port 3. a 1 in this location brings the comparator outputs to p34 and p37, and a 0 releases th e port to its standa rd i/o configuration. port 1 output mode (d1) bit 1 controls the output mode of port 1. a 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain. d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 0 p34, p37 standard output* 1 p34, p37 comparator output port 1 0: open-drain 1: push-pull* port 0 0: open-drain 1: push-pull* reserved (must be 1) * default setting after reset
zgp323h product specification ps023806-0506 functional description 50 port 0 output mode (d2) bit 2 controls the output mode of port 0. a 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain. stop-mode recovery register (smr) this register selects the clock divide value and determines the mode of stop mode recov- ery ( figure 31 ). all bits are write only except bit 7, which is read only. bit 7 is a flag bit that is hardware set on the condition of stop recovery and reset by a power-on cycle. bit 6 controls whether a low level or a hi gh level at the xor-gate input ( figure 33 on page 53) is required from the recovery source. bit 5 cont rols the reset delay after recovery. bits d2, d3, and d4 of the smr register specify the so urce of the stop mode recovery signal. bits d0 determines if sclk/tclk are divided by 16 or not. the smr is located in bank f of the expanded register group at address 0bh . smr(0f)0bh d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0 off * * 1 on reserved (must be 0)
zgp323h product specification ps023806-0506 functional description 51 figure 31. stop mode recovery register sclk/tclk divide-by-16 select (d0) d0 of the smr controls a divide-by-16 prescaler of sclk/tclk ( figure 32 ). this con- trol selectively reduces device power consumption during normal processor execution (sclk control) and/or halt mode (where tclk sources interrupt logic). after stop mode recovery, this bit is set to a 0. figure 32. sclk circuit stop-mode recovery source 000 por only * 001 reserved 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 stop delay 0 off 1 on * * * * stop recovery level * * * 0 low * 1 high stop flag 0 por * 1 stop recovery * * * default after power on reset or watch-dog reset * * default setting after re set and stop mode recovery * * * at the xor gate input * * * * default setting after reset. must be 1 if using a crystal or resonator clock source. scl tclk smr, d0 2 osc 16
zgp323h product specification ps023806-0506 functional description 52 stop-mode recovery source (d2, d3, and d4) these three bits of the smr specify the wake-up source of the stop recovery ( figure 33 and table 14 ). stop-mode recovery register 2?smr2(f)0dh table 13 lists and briefly describes the fields for this register. table 13. smr2(f)0dh:stop mode recovery register 2* field bit position value description reserved 7------- 0 reserved (must be 0) recovery level -6------ w0 ? 1 low high reserved --5----- 0 reserved (must be 0) source ---432-- w000 ? 001 010 011 100 101 110 111 a. por only b. nand of p23?p20 c. nand of p27?p20 d. nor of p33?p31 e. nand of p33?p31 f. nor of p33?p31, p00, p07 g. nand of p33?p31, p00, p07 h. nand of p33?p31, p22?p20 reserved ------10 00 reserved (must be 0) notes: * port pins configured as outputs are ignored as a smr recovery source. ? indicates the value upon power-on reset
zgp323h product specification ps023806-0506 functional description 53 figure 33. stop mode recovery source smr2 d4 d3 d2 100 smr2 d4 d3 d2 111 smr d4 d3 d2 010 smr d4 d3 d2 111 smr d4 d3 d2 101 smr d4 d3 d2 100 smr d4 d3 d2 011 smr d4d3d2 000 smr d4 d3 d2 110 vcc p31 p32 p33 p27 p20 p23 p20 p27 smr2 d4 d3 d2 001 smr2 d4 d3 d2 000 smr2 d4 d3 d2 010 smr2 d4 d3 d2 011 smr2 d4 d3 d2 101 smr2 d4 d3 d2 110 vcc p20 p23 p20 p27 p31 p32 p33 p31 p32 p33 p31 p32 p33 p00 p07 p31 p32 p33 p00 p07 p31 p32 p33 p20 p21 p22 smr d6 smr2 d6 to reset and wdt circuitry (active
zgp323h product specification ps023806-0506 functional description 54 any port 2 bit defined as an output drives th e corresponding input to the default state. this condition allows the remainin g inputs to control the and/ or function. refer to smr2 register on page 55 fo r other recover sources. stop mode recovery delay select (d5) this bit, if low, disables the t por delay after stop mode recovery. the default configu- ration of this bit is 1. if the ?fast? wake up is selected, the stop mode recovery source must be kept active for at least 5 tpc. this bit must be set to 1 if using a crystal or resonator clock source. the t por delay allows the clock source to stabil ize before execu ting instructions. stop mode recovery edge select (d6) a 1 in this bit position indicates that a high level on any one of the recovery sources wakes the device from stop mode. a 0 indicates low level recovery. the default is 0 on por. cold or warm start (d7) this bit is read only. it is set to 1 when th e device is recovered from stop mode. the bit is set to 0 when the device reset is ot her than stop mode recovery (smr). table 14. stop mode recovery source smr:432 operation d4 d3 d2 description of action 0 0 0 por and/or external reset recovery 001reserved 0 1 0 p31 transition 0 1 1 p32 transition 1 0 0 p33 transition 1 0 1 p27 transition 1 1 0 logical nor of p20 through p23 1 1 1 logical nor of p20 through p27 note: note:
zgp323h product specification ps023806-0506 functional description 55 stop mode recovery register 2 (smr2) this register determines the mode of stop mode recovery for smr2 ( figure 34 ). smr2(0f)dh figure 34. stop mode recovery register 2 ((0f)dh:d2?d4, d6 write only) if smr2 is used in conjunctio n with smr, either of the sp ecified events causes a stop mode recovery. port pins configured as outputs are ignore d as an smr or smr2 recovery source. for example, if the nand or p23?p20 is selected as the recovery source and p20 is config- ured as an output, the remaining smr pins (p23?p21) form the nand equation. d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 0) stop-mode recovery source 2 000 por only * 001 nand p20, p21, p22, p23 010 nand p20, p21, p22, p23, p24, p25, p26, p27 011 nor p31, p32, p33 100 nand p31, p32, p33 101 nor p31, p32, p33, p00, p07 110 nand p31, p32, p33, p00, p07 111 nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level * * 0low * 1high reserved (must be 0) note: if used in conjunction with smr, either of t he two specified events causes a stop-mode recovery. * default setting after reset * * at the xor gate input note:
zgp323h product specification ps023806-0506 functional description 56 watch-dog timer mode register (wdtmr) the watch-dog timer (wdt) is a retrigge rable one-shot timer that resets the z8 ? cpu if it reaches its terminal count. the wdt must initially be enabled by executing the wdt instruction. on subsequent ex ecutions of the wdt instructio n, the wdt is refreshed. the wdt circuit is driven by an on-board rc-oscillator. the wdt instruction affects the zero (z), sign (s), and overflow (v) flags. the por clock source the internal rc-oscillator. bits 0 and 1 of the wdt register control a tap circuit that determines the minimum tim eout period. bit 2 determines whether the wdt is active during halt, and bit 3 determ ines wdt activity during stop. bits 4 through 7 are reserved ( figure 35 ). this register is accessible only during the first 60 pro- cessor cycles (120 xtal clocks) from the exec ution of the first instruction after power- on-reset, watch-dog reset, or a stop-mode recovery ( figure 34 ). after this point, the register cannot be modified by any means (intentional or otherwise). the wdtmr cannot be read. the register is located in bank f of the expanded register group at address location 0fh . it is organized as shown in figure 35 . wdtmr(0f)0fh figure 35. watch-dog timer mode register (write only) wdt time select (d0, d1) this bit selects the wdt time period . it is configured as indicated in table 15 . d7 d6 d5 d4 d3 d2 d1 d0 wdt tap int rc osc 00 5 ms min. 01* 10 ms min. 10 20 ms min. 11 80 ms min. wdt during halt 0off 1on * wdt during stop 0off 1on * reserved (must be 0) * default setting after reset
zgp323h product specification ps023806-0506 functional description 57 wdtmr during halt (d2) this bit determines whether or not the wdt is active during halt mode. a 1 indicates active during halt. the default is 1. see figure 36 . figure 36. resets and wdt table 15. watch-dog timer time select d1 d0 timeout of internal rc-oscillator 005ms min. 0 1 10ms min. 1 0 20ms min. 1 1 80ms min. - * clr1 and clr2 enable the wdt/por and 18 clock reset timers respectively upon a low-to- + from stop mode recovery stop delay select 5 clock *clr2 18 clock rese wdt por 5 ms 10 ms 20 ms 80 cl *clr wdt/por counter internal rc wdt v dd low vbo v dd interna l rese t 12-ns glitch xtal
zgp323h product specification ps023806-0506 functional description 58 wdtmr during stop (d3) this bit determines whether or not the wd t is active during stop mode. because the xtal clock is stopped during stop mode, the on-board rc has to be selected as the clock source to the wdt/por counter. a 1 indi cates active during stop. the default is 1. eprom selectable options there are seven eprom selectable options to choose from based on rom code require- ments. these options are listed in table 16 . voltage brown-out/standby an on-chip voltage comparator checks that the v dd is at the required level for correct operation of the device. reset is globally driven when v dd falls below v bo . a small drop in v dd causes the xtal1 and xtal2 circuitry to stop the crystal or resonator clock. if the v dd is allowed to stay above v ram , the ram content is preserved. when the power level is returned to above v bo , the device performs a por and functions normally. low-voltage detection register?lvd(d)0ch voltage detection does not work at stop mode. it must be disabled during stop mode in order to reduce current. table 16. eprom selectable options port 00?03 pull-ups on/off port 04?07 pull-ups on/off port 10?13 pull-ups on/off port 14?17 pull-ups on/off port 20?27 pull-ups on/off eprom protection on/off watch-dog timer at power-on reset on/off note:
zgp323h product specification ps023806-0506 functional description 59 do not modify register p01m while checkin g a low-voltage condition. switching noise of both ports 0 and 1 together might trigger the lvd flag. voltage detection and flags the voltage detection register (lvd, register 0ch at the expanded register bank 0dh ) offers an option of monitoring the v cc voltage. the voltage detec tion is enabled when bit 0 of lvd register is set. once volta ge detection is enabled, the the v cc level is monitored in real time. the flags in the lvd register va lid 20us after voltage detection is enabled. the hvd flag (bit 2 of the lvd register) is set only if v cc is higher than v hvd. the lvd flag (bit 1 of the lvd register) is set only if v cc is lower than the v lvd . when voltage detection is enabled, the lvd flag also trig gers irq5. the irq bit 5 latches the low volt- age condition until it is cleared by instructions or reset. the irq5 interrupt is served if it is enabled in the imr register. ot herwise, bit 5 of irq register is latched as a flag only. if it is necessary to receive an lvd interrupt up on power-up at an operating voltage lower than the low battery detect th reshold, enable interrupts usin g the enable interrupt instruc- tion (ei) prior to enablin g the voltage detection. expanded register file control registers (0d) the expanded register file control registers (0d) are depicted in figure 37 through figure 41 . field bit position description lvd 76543--- reserved no effect -----2-- r 1 0* hvd flag set hvd flag reset ------1- r 1 0* lvd flag set lvd flag reset -------0 r/w 1 0* enable vd disable vd * default after por note: notes:
zgp323h product specification ps023806-0506 functional description 60 figure 37. tc8 control register ((0d)o0h: read/write except where noted) ctr0(0d)00h d7 d6 d5 d4 d3 d2 d1 d0 0 p34 as port output * 1 timer8 output 0disable t8 tim eout interrupt * * 1 enable t8 timeout interrupt 0 disable t8 data capture interrupt * * 1 enable t8 data capture interrupt 00 sclk on t8* * 01 sclk/2 on t8 10 sclk/4 on t8 11 sclk/8 on t8 r 0 no t8 counte r timeout * * r 1 t8 counter timeout occurred w 0 no effect w 1 reset flag to 0 0 modulo-n * 1 single pass r 0 t8 disabled * r1 t8 enabled w0 stop t8 w1 enable t8 * default setting after reset. * * default setting after reset.. not reset with a stop-mode recovery.
zgp323h product specification ps023806-0506 functional description 61 figure 38. t8 and t16 common control functions ((0d)01h: read/write) ctr1(0d)01h d7 d6 d5 d4 d3 d2 d1 d0 transmit mode* r/w 0 t16_out is 0 initially 1 t16_out is 1 initially demodulation mode r 0 no falling edge detection r 1 falling edge detection w 0 no effect w 1 reset flag to 0 transmit mode* r/w 0 t8_out is 0 initially* 1 t8_out is 1 initially demodulation mode r 0 no rising edge detection r 1 rising edge detection w 0 no effect w 1 reset flag to 0 transmit mode* 0 0 normal operation* 0 1 ping-pong mode 1 0 t16_out = 0 1 1 t16_out = 1 demodulation mode 0 0 no filter 0 1 4 sclk cycle filter 1 0 8 sclk cycle filter 11reserved transmit mode/t8/t16 logic 0 0 and** 01or 1 0 nor 1 1 nand demodulation mode 0 0 falling edge detection 0 1 rising edge detection 1 0 both edge detection 11reserved transmit mode* 0 p36 as port output * 1 p36 as t8/t16_out demodulation mode 0 p31 as demodulator input 1 p20 as demodulator input transmit/demodulation mode 0 transmit mode * 1 demodulation mode * default setting after reset **default setting after reset.. not reset with a stop-mode recovery.
zgp323h product specification ps023806-0506 functional description 62 take care in differentiating the transmit mode from demodulation mode. depending on which of these two modes is operating, the ctr1 bit has different functions. changing from one mode to another cannot be performed without disabling the counter/ timers. ctr2(0d)02h figure 39. t16 control register ((0d) 2h: read/write except where noted) ctr3(0d)03h d7 d6 d5 d4 d3 d2 d1 d0 0 p35 is port output * 1 p35 is tc16 output 0 disable t16 timeout interrupt 1 enable t16 timeout interrupt 0 disable t16 data capture interrupt 1 enable t16 data capture interrupt 0 0 sclk on t16 0 1 sclk/2 on t16 1 0 sclk/4 on t16 1 1 sclk/8 on t16 r 0 no t16 timeout r 1 t16 timeout occurs w0no effect w 1 reset flag to 0 transmit mode 0 modulo-n for t16 1 single pass for t16 demodulator mode 0 t16 recognizes edge 1 t16 does not recognize edge r 0 t16 disabled * r 1 t16 enabled w0stop t16 w1enable t16 * default setting after reset ** default setting after reset. not reset with a stop- mode recovery. notes:
zgp323h product specification ps023806-0506 functional description 63 figure 40. t8/t16 control register (0d)03h: read/write (except where noted) lvd(0d)0ch d7 d6 d5 d4 d3 d2 d1 d0 reserved no effect when written always reads 11111 sync mode 0* disable sync mode** 1 enable sync mode t 8 enable r 0* t 8 disabled r 1 t 8 enabled w0 stop t 8 w1 enable t 8 t 16 enable r 0* t 16 disabled r 1 t 16 enabled w 0 stop t 16 w 1 enable t 16 * default setting after reset. ** default setting after reset. not reset with a stop mode recovery. d7 d6 d5 d4 d3 d2 d1 d0
zgp323h product specification ps023806-0506 functional description 64 figure 41. voltage detection register do not modify register p01m while checkin g a low-voltage condition. switching noise of both ports 0 and 1 together might trigger the lvd flag. expanded register file control registers (0f) the expanded register file control registers (0f) are depicted in figures 42 through figure 55 . pcon(0f)00h voltage detection 0: disable * 1: enable lvd flag (read only) 0: lvd flag reset * 1: lvd flag set hvd flag (read only) 0: hvd flag reset * 1: hvd flag set reserved (must be 0) * default setting after reset. d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 0 p34, p37 standard output * 1 p34, p37 comparator output port 1 0: open-drain 1: push-pull* port 0 0: open-drain 1: push-pull * reserved (must be 1) * default setting after reset note:
zgp323h product specification ps023806-0506 functional description 65 figure 42. port configuration register (pcon)(0f)00h: write only) smr(0f)0bh figure 43. stop mode recovery register ((0f)0bh: d6?d0=write only, d7=read only) d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0 off * 1 on reserved (must be 0) stop-mode recovery source 000 por only * 001 reserved 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0?3 111 p2 nor 0?7 stop delay 0off 1 on * * * * stop recovery level * * * 0 low * 1high stop flag 0 por * * * * * 1 stop recovery * * * default setting after reset * * set after stop mode recovery * * * at the xor gate input * * * * default setting after reset. must be 1 if using a crystal or resonator clock source. * * * * * default setting afte r power on reset. not reset with a stop mode recovery.
zgp323h product specification ps023806-0506 functional description 66 smr2(0f)0dh figure 44. stop mode recovery register 2 ((0f)0dh:d2?d4, d6 write only) d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 0) stop-mode recovery source 2 000 por only * 001 nand p20, p21, p22, p23 010 nand p20, p21, p22, p23, p24, p25, p26, p27 011 nor p31, p32, p33 100 nand p31, p32, p33 101 nor p31, p32, p33, p00, p07 110 nand p31, p32, p33, p00, p07 111 nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level * * 0low 1high reserved (must be 0) note: if used in conjunction with smr, either of t he two specified events causes a stop-mode recovery. * default setting after reset. not reset with a stop mode recovery. * * at the xor gate input
zgp323h product specification ps023806-0506 functional description 67 wdtmr(0f)0fh figure 45. watch-dog timer register ((0f) 0fh: write only) standard control registers r246 p2m(f6h) figure 46. port 2 mode register (f6h: write only) d7 d6 d5 d4 d3 d2 d1 d0 wdt tap int rc osc 00 5 ms min. 01* 10 ms min. 10 20 ms min. 11 80 ms min. wdt during halt 0off 1on * wdt during stop 0off 1on * reserved (must be 0) * default setting after reset. not reset with a stop mode recovery. d7 d6 d5 d4 d3 d2 d1 d0 p27?p20 i/o definition 0 defines bit as output 1 defines bit as input * * default setting after reset. not reset with a stop mode recovery.
zgp323h product specification ps023806-0506 functional description 68 r247 p3m(f7h) figure 47. port 3 mode register (f7h: write only) r248 p01m(f8h) d7 d6 d5 d4 d3 d2 d1 d0 0: port 2 open drain * 1: port 2 push-pull 0= p31, p32 digital mode* 1= p31, p32 analog mode reserved (must be 0) * default setting after reset. not reset with a stop mode recovery. d7 d6 d5 d4 d3 d2 d1 d0 p00?p03 mode 0: output 1: input * reserved (must be 0) reserved (must be 1)
zgp323h product specification ps023806-0506 functional description 69 figure 48. port 0 and 1 mode register (f8h: write only) r249 ipr(f9h) p17?p10 mode 0: byte output 1: byte input* reserved (must be 0) p07?p04 mode 0: output 1: input * reserved (must be 0) * default setting after reset; only p00, p01 and p07 are available on 20-pin configurations. d7 d6 d5 d4 d3 d2 d1 d0 interrupt gr oup priority 000 reserved 001 c > a > b 010 a > b >c 011 a > c > b 100 b > c > a 101 c > b > a 110 b > a > c 111 reserved
zgp323h product specification ps023806-0506 functional description 70 figure 49. interrupt priority register (f9h: write only) r250 irq(fah) figure 50. interrupt request register (fah: read/write) irq1, irq4, priority (group c) 0: irq1 > irq4 1: irq4 > irq1 irq0, irq2, priority (group b) 0: irq2 > irq0 1: irq0 > irq2 irq3, irq5, priority (group a) 0: irq5 > irq3 1: irq3 > irq5 reserved; must be 0 d7 d6 d5 d4 d3 d2 d1 d0 irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = t16 irq4 = t8 irq5 = lvd inter edge p31 p32 = 00 p31 p32 = 01 p31 p32 = 10 p31 p32 = 11
zgp323h product specification ps023806-0506 functional description 71 r251 imr(fbh) figure 51. interrupt mask register (fbh: read/write) r252 flags(fch) figure 52. flag register (fch: read/write) d7 d6 d5 d4 d3 d2 d1 d0 1 enables irq5?irq0 (d0 = irq0) reserved (must be 0) 0 master interrupt disable * 1 master interrupt enable * * * default setting after reset * * only by using ei, di instruction; di is required before changing the imr register d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign tag zero flag carry flag
zgp323h product specification ps023806-0506 functional description 72 r253 rp(fdh) figure 53. register pointer (fdh: read/write) r254 sph(feh) figure 54. stack pointer high (feh: read/write) r255 spl(ffh) figure 55. stack pointer low (ffh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 expanded register bank pointer working register pointer default setting afte r reset = 0000 0000 d7 d6 d5 d4 d3 d2 d1 d0 general-purpose register d7 d6 d5 d4 d3 d2 d1 d0 stack pointer low byte (sp7?sp0)
zgp323h product specification ps023806-0506 electrical characteristics 73 electrical characteristics absolute maximum ratings stresses greater than those listed in table 17 might cause permanent damage to the device. this rating is a stress rating only. functiona l operation of the de vice at any condition above those indicated in the operational secti ons of these specifications is not implied. exposure to absolute maximum rating conditio ns for an extended period might affect device reliability. standard test conditions the characteristics listed in th is product specification apply for standard test conditions as noted. all voltages are referenced to gnd. po sitive current flows into the referenced pin (see figure 56 ). table 17. absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias ?40 125 c 1 storage temperature ?65 +150 c voltage on any pin with respect to v ss ?0.3 7.0 v 2 voltage on v dd pin with respect to v ss ?0.3 7.0 v maximum current on input and/or inactive output pin ?5 +5 a maximum output current from active output pin ?25 +25 ma maximum current into v dd or out of v ss 75 ma notes: 1. see ordering information. 2. this voltage applies to all pins except the following: v dd , p32, p33 and reset .
zgp323h product specification ps023806-0506 electrical characteristics 74 figure 56. test load diagram capacitance table 18 lists the capacitances. dc characteristics table 18. capacitance parameter maximum input capacitance 12pf output capacitance 12pf i/o capacitance 12pf note: t a = 25 c, v cc = gnd = 0 v, f = 1.0 mhz, unmeasured pins returned to gnd table 19. gp323hs dc characteristics t a =0c to +70c units conditions notes symbol parameter v cc min typ(7) max v cc supply voltage 2.0 5.5 v see note 5 5 v ch clock input high voltage 2.0-5.5 0.8 v cc v cc +0.3 v driven by external clock generator v cl clock input low voltage 2.0-5.5 v ss ?0.3 0.4 v driven by external clock generator v ih input high voltage 2.0-5.5 0.7 v cc v cc +0.3 v v il input low voltage 2.0-5.5 v ss ?0.3 0.2 v cc v v oh1 output high voltage 2.0-5.5 v cc ?0.4 v i oh = ?0.5ma from output under test 150pf
zgp323h product specification ps023806-0506 electrical characteristics 75 v oh2 output high voltage (p36, p37, p00, p01) 2.0-5.5 v cc ?0.8 v i oh = ?7ma v ol1 output low voltage 2.0-5.5 0.4 v i ol = 4.0ma v ol2 output low voltage (p00, p01, p36, p37) 2.0-5.5 0.8 v i ol = 10ma v offset comparator input offset voltage 2.0-5.5 25 mv v ref comparator reference voltage 2.0-5.5 0 v cc 1.75 v i il input leakage 2.0-5.5 ?1 1 av in = 0v, v cc pull-ups disabled r pu pull-up resistance 2.0v 225 675 k v in = 0v; pullups selected by mask option 3.6v 75 275 k 5.0v 40 160 k i ol output leakage 2.0-5.5 ?1 1 av in = 0v, v cc i cc supply current 2.0v 3.6v 5.5v 1 5 10 3 10 15 ma ma ma at 8.0 mhz at 8.0 mhz at 8.0 mhz 1, 2 1, 2 1, 2 i cc1 standby current (halt mode) 2.0v 3.6v 5.5v 0.5 0.8 1.3 1.6 2.0 3.2 ma ma ma v in = 0v, clock at 8.0mhz v in = 0v, clock at 8.0mhz v in = 0v, clock at 8.0mhz 1, 2, 6 1, 2, 6 1, 2, 6 i cc2 standby current (stop mode) 2.0v 3.6v 5.5v 2.0v 3.6v 5.5v 1.6 1.8 1.9 5 8 15 8 10 12 20 30 45 a a a a a a v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt is running v in = 0 v, v cc wdt is running v in = 0 v, v cc wdt is running 3 3 3 3 3 3 i lv standby current (low voltage) 1.2 6 a measured at 1.3v 4 v bo v cc low voltage protection 1.9 2.0 v 8mhz maximum ext. clk freq. v lvd v cc low voltage detection 2.4 v v hvd vcc high voltage detection 2.7 v table 19. gp323hs dc characteristics (continued) t a =0c to +70c units conditions notes symbol parameter v cc min typ(7) max
zgp323h product specification ps023806-0506 electrical characteristics 76 notes: 1. all outputs unloaded, inputs at rail. 2. cl1 = cl2 = 100 pf. 3. oscillator stopped. 4. oscillator stops when v cc falls below v bo limit. 5. it is strongly recommended to add a filter capacitor (minimum 0.1 f), physically close to vcc and v ss pins if operating voltage fluctuations are anticipated, such as those result ing from driving an infrared led. 6. comparator and timers are on. interrupt disabled. 7. typical values shown are at 25 degrees c. table 20. gp323he dc characteristics t a = -40c to +105c units conditions notes symbol parameter v cc min typ(7) max v cc supply voltage 2.0 5.5 v see note 5 5 v ch clock input high voltage 2.0-5.5 0.8 v cc v cc +0.3 v driven by external clock generator v cl clock input low voltage 2.0-5.5 v ss ?0.3 0.4 v driven by external clock generator v ih input high voltage 2.0-5.5 0.7 v cc v cc +0.3 v v il input low voltage 2.0-5.5 v ss ?0.3 0.2 v cc v v oh1 output high voltage 2.0-5.5 v cc ?0.4 v i oh = ?0.5ma v oh2 output high voltage (p36, p37, p00, p01) 2.0-5.5 v cc ?0.8 v i oh = ?7ma v ol1 output low voltage 2.0-5.5 0.4 v i ol = 4.0ma v ol2 output low voltage (p00, p01, p36, p37) 2.0-5.5 0.8 v i ol = 10ma v offset comparator input offset voltage 2.0-5.5 25 mv v ref comparator reference voltage 2.0-5.5 0 v dd -1.75 v i il input leakage 2.0-5.5 ?1 1 av in = 0v, v cc pull-ups disabled r pu pull-up resistance 2.0v 200.0 700.0 k v in = 0v; pullups selected by mask option 3.6v 50.0 300.0 k 5.0v 25.0 175.0 k i ol output leakage 2.0-5.5 ?1 1 av in = 0v, v cc i cc supply current 2.0v 3.6v 5.5v 1 5 10 3 10 15 ma ma ma at 8.0 mhz at 8.0 mhz at 8.0 mhz 1, 2 1, 2 1, 2 table 19. gp323hs dc characteristics (continued) t a =0c to +70c units conditions notes symbol parameter v cc min typ(7) max
zgp323h product specification ps023806-0506 electrical characteristics 77 i cc1 standby current (halt mode) 2.0v 3.6v 5.5v 0.5 0.8 1.3 1.6 2.0 3.2 ma ma ma v in = 0v, clock at 8.0mhz v in = 0v, clock at 8.0mhz v in = 0v, clock at 8.0mhz 1, 2, 6 1, 2, 6 1, 2, 6 i cc2 standby current (stop mode) 2.0v 3.6v 5.5v 2.0v 3.6v 5.5v 1.6 1.8 1.9 5 8 15 12 15 18 30 40 60 a a a a a a v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt is running v in = 0 v, v cc wdt is running v in = 0 v, v cc wdt is running 3 3 3 3 3 3 i lv standby current (low voltage) 1.2 6 a measured at 1.3v 4 v bo v cc low voltage protection 1.9 2.15 v 8mhz maximum ext. clk freq. v lvd v cc low voltage detection 2.4 v v hvd vcc high voltage detection 2.7 v notes: 1. all outputs unloaded, inputs at rail. 2. cl1 = cl2 = 100 pf. 3. oscillator stopped. 4. oscillator stops when v cc falls below v bo limit. 5. it is strongly recommended to add a filter capacitor (minimum 0.1 f), physically close to vcc and v ss pins if operating voltage fluctuations are anticipated, such as those result ing from driving an infrared led. 6. comparator and timers are on. interrupt disabled. 7. typical values shown are at 25 degrees c. table 21. gp323ha dc characteristics t a = -40c to +125c units conditions notes symbol parameter v cc min typ(7) max v cc supply voltage 2.0 5.5 v see note 5 5 v ch clock input high voltage 2.0-5.5 0.8 v cc v cc +0.3 v driven by external clock generator v cl clock input low voltage 2.0-5.5 v ss ?0.3 0.4 v driven by external clock generator table 20. gp323he dc characteristics (continued) t a = -40c to +105c units conditions notes symbol parameter v cc min typ(7) max
zgp323h product specification ps023806-0506 electrical characteristics 78 v ih input high voltage 2.0-5.5 0.7 v cc v cc +0.3 v v il input low voltage 2.0-5.5 v ss ?0.3 0.2 v cc v v oh1 output high voltage 2.0-5.5 v cc ?0.4 v i oh = ?0.5ma v oh2 output high voltage (p36, p37, p00, p01) 2.0-5.5 v cc ?0.8 v i oh = ?7ma v ol1 output low voltage 2.0-5.5 0.4 v i ol = 4.0ma v ol2 output low voltage (p00, p01, p36, p37) 2.0-5.5 0.8 v i ol = 10ma v offset comparator input offset voltage 2.0-5.5 25 mv v ref comparator reference voltage 2.0-5.5 0 v dd -1.75 v i il input leakage 2.0-5.5 ?1 1 av in = 0v, v cc pull-ups disabled r pu pull-up resistance 2.0v 200 700 k v in = 0v; pullups selected by mask option 3.6v 50 300 k 5.0v 25 175 k i ol output leakage 2.0-5.5 ?1 1 av in = 0v, v cc i cc supply current 2.0v 3.6v 5.5v 1 5 10 3 10 15 ma ma ma at 8.0 mhz at 8.0 mhz at 8.0 mhz 1, 2 1, 2 1, 2 i cc1 standby current (halt mode) 2.0v 3.6v 5.5v 0.5 0.8 1.3 1.6 2.0 3.2 ma ma ma v in = 0v, clock at 8.0mhz v in = 0v, clock at 8.0mhz v in = 0v, clock at 8.0mhz 1, 2, 6 1, 2, 6 1, 2, 6 i cc2 standby current (stop mode) 2.0v 3.6v 5.5v 2.0v 3.6v 5.5v 1.6 1.8 1.9 5 8 15 15 20 25 30 40 60 a a a a a a v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt not running v in = 0 v, v cc wdt is running v in = 0 v, v cc wdt is running v in = 0 v, v cc wdt is running 3 3 3 3 3 3 i lv standby current (low voltage) 1.2 6 a measured at 1.3v 4 v bo v cc low voltage protection 1.9 2.15 v 8mhz maximum ext. clk freq. table 21. gp323ha dc characteristics (continued) t a = -40c to +125c units conditions notes symbol parameter v cc min typ(7) max
zgp323h product specification ps023806-0506 electrical characteristics 79 v lvd v cc low voltage detection 2.4 v v hvd vcc high voltage detection 2.7 v notes: 1. all outputs unloaded, inputs at rail. 2. cl1 = cl2 = 100 pf. 3. oscillator stopped. 4. oscillator stops when v cc falls below v bo limit. 5. it is strongly recommended to add a filter capacitor (minimum 0.1 f), physically close to vcc and v ss pins if operating voltage fluctuations are anticipated, such as those result ing from driving an infrared led. 6. comparator and timers are on. interrupt disabled. 7. typical values shown are at 25 degrees c. table 22. eprom/otp characteristics symbol parameter min. typ. max. unit notes erase time 15 minutes 1,3 data retention @ use years 10 years 2 program/erase endurance 100 cycles 1 notes: 1. for windowed cerdip package only. 2. standard: 0c to 70c; extended: -40c to +105c; automotive: -40c to +125c. determined using the arrhenius model, which is an industry standard for estimating data retention of floating gate technologies: af = exp[(ea/k)*(1/tuse - 1/tstress)] where: ea is the intrinsic activati on energy (ev; typ. 0.8) k is boltzman?s constant (8.67 x 10-5 ev/k) k = -273.16c tuse = use temperature in k tstress = stress temperature in k 3. at a stable uv la mp output of 20mw/cm 2 table 21. gp323ha dc characteristics (continued) t a = -40c to +125c units conditions notes symbol parameter v cc min typ(7) max
zgp323h product specification ps023806-0506 electrical characteristics 80 ac characteristics figure 57 and table 23 describe the alternating current (ac) characteristics. figure 57. ac timing diagram clock stop mode recovery source clock setup 1 22 3 3 t in 7 4 5 6 7 irq n 8 9 11 10
zgp323h product specification ps023806-0506 electrical characteristics 81 table 23. ac characteristics t a =0c to +70c (s) ?40c to +105c (e) ?40c to +125c (a) 8.0mhz watch- dog timer mode register (d1, d0) no symbol parameter v cc minimum maximum units notes 1 tpc input clock period 2.0?5.5 121 dc ns 1 2 trc,tfc clock input rise and fall times 2.0?5.5 25 ns 1 3 twc input clock width 2.0?5.5 37 ns 1 4 twtinl timer input low width 2.0 5.5 100 70 ns 1 5 twtinh timer input high width 2.0?5.5 3tpc 1 6 tptin timer input period 2.0?5.5 8tpc 1 7 trtin,tftin timer input rise and fall timers 2.0?5.5 100 ns 1 8 twil interrupt request low time 2.0 5.5 100 70 ns 1, 2 9 twih interrupt request input high time 2.0?5.5 5tpc 1, 2 10 twsm stop-mode recovery width spec 2.0?5.5 12 5tpc ns 3 4 11 tost oscillator start-up time 2.0?5.5 5tpc 4 12 twdt watch-dog timer delay time 2.0?5.5 2.0?5.5 2.0?5.5 2.0?5.5 5 10 20 80 ms ms ms ms 0, 0 0, 1 1, 0 1, 1 13 t por power-on reset 2.0?5.5 2.5 10 ms notes: 1. timing reference uses 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. 2. interrupt request through port 3 (p33?p31). 3. smr ? d5 = 1. 4. smr ? d5 = 0.
zgp323h product specification ps023806-0506 packaging 82 packaging package information for all versio ns of zgp323h is depicted in figures 59 through figure 68 . figure 58. 20-pin cdip package
zgp323h product specification ps023806-0506 packaging 83 figure 59. 20-pin pdip package diagram figure 60. 20-pin soic package diagram
zgp323h product specification ps023806-0506 packaging 84 figure 61. 20-pin ssop package diagram
zgp323h product specification ps023806-0506 packaging 85 figure 62. 28-pin soic package diagram
zgp323h product specification ps023806-0506 packaging 86 figure 63. 28-pin cdip package diagram figure 64. 28-pin pdip package diagram
zgp323h product specification ps023806-0506 packaging 87 figure 65. 28-pin ssop package diagram figure 66. 40-pin pdip package diagram symbol a a1 b c a2 e millimeter inch min max min max 1.73 0.05 1.68 0.25 5.20 0.65 typ 0.09 10.07 7.65 0.63 1.86 0.0256 typ 0.13 10.20 1.73 7.80 5.30 1.99 0.21 1.78 0.75 0.068 0.002 0.066 0.010 0.205 0.004 0.397 0.301 0.025 0.073 0.005 0.068 0.209 0.006 0.402 0.307 0.030 0.078 0.008 0.070 0.015 0.212 0.008 0.407 0.311 0.037 0.38 0.20 10.33 5.38 7.90 0.95 nom nom d e h l controlling dimensions: mm leads are coplanar within .004 inches. h c detail a e d 28 15 114 seating plane a2 e a q1 a1 b l 0 - 8 detail 'a'
zgp323h product specification ps023806-0506 packaging 88 figure 67. 40-pin cdip package diagram
zgp323h product specification ps023806-0506 packaging 89 figure 68. 48-pin ssop package design check with zilog on the actual bonding diagram and coordinate for chip-on-board assembly. controlling dimensions : mm leads are coplanar within .004 inch d e h a1 a2 a e seating plane b 48 25 c detail a 0-8? l 1 24 note:
zgp323h product specification ps023806-0506 ordering information 90 ordering information 32 kb standard temperature: 0 to +70c part number description p art number description zgp323hsh4832 g 48-pin ssop 32k otp zgp323hss2832g 28-pin soic 32k otp zgp323hsp4032g 40-pin pdip 32k otp zgp323hsh2032g 20-pin ssop 32k otp zgp323hsk2832e 28-pin cdip 32k otp zgp323hsk2032e 20-pin cdip 32k otp zgp323hsk4032e 40-pin cdip 32k otp zgp323hsp2032g 20-pin pdip 32k otp zgp323hsh2832 g 28-pin ssop 32k otp zgp323hss2032g 20-pin soic 32k otp zgp323hsp2832g 28-pin pdip 32k otp 32 kb extended temperature: ?40 to +105c part number description p art number description zgp323heh4832 g 48-pin ssop 32k otp zgp323hes2832g 28-pin soic 32k otp zgp323hep4032g 40-pin pdip 32k otp zgp323heh2032g 20-pin ssop 32k otp zgp323heh2832 g 28-pin ssop 32k otp zgp323hep2032g 20-pin pdip 32k otp zgp323hep2832g 28-pin pdip 32k otp zgp323hes2032g 20-pin soic 32k otp 3 2kb automotive temperature: ?40 to +125c part number description p art number description zgp323hah4832 g 48-pin ssop 32k otp zgp323has2832g 28-pin soic 32k otp zgp323hap4032g 40-pin pdip 32k otp zgp323hah2032g 20-pin ssop 32k otp zgp323hah2832 g 28-pin ssop 32k otp zgp323hap2032g 20-pin pdip 32k otp zgp323hap2832g 28-pin pdip 32k otp zgp323has2032g 20-pin soic 32k otp
zgp323h product specification ps023806-0506 ordering information 91 16 kb standard temperature: 0 to +70c part number description part number description zgp323hsh4816 g 48-pin ssop 16k otp zgp323hss2816g 28-pin soic 16k otp zgp323hsp4016g 40-pin pdip 16k otp z gp323hsh2016g 20-pin ssop 16k otp zgp323hsh2816 g 28-pin ssop 16k otp zgp323hsp2016g 20-pin pdip 16k otp zgp323hsp2816g 28-pin pdip 16k otp z gp323hss2016g 20-pin soic 16k otp 16 kb extended temperature: ?40 to +105c part number description part number description zgp323heh4816 g 48-pin ssop 16k otp zgp323hes2816g 28-pin soic 16k otp zgp323hep4016g 40-pin pdip 16k otp z gp323heh2016g 20-pin ssop 16k otp zgp323heh2816 g 28-pin ssop 16k otp zgp323hep2016g 20-pin pdip 16k otp zgp323hep2816g 28-pin pdip 16k otp z gp323hes2016g 20-pin soic 16k otp 16 kb automotive temperature: ?40 to +125c part number description part number description zgp323hah4816 g 48-pin ssop 16k otp zgp323has2816g 28-pin soic 16k otp zgp323hap4016g 40-pin pdip 16k otp z gp323hah2016g 20-pin ssop 16k otp zgp323hah2816 g 28-pin ssop 16k otp zgp323hap2016g 20-pin pdip 16k otp zgp323hap2816g 28-pin pdip 16k otp z gp323has2016g 20-pin soic 16k otp
zgp323h product specification ps023806-0506 ordering information 92 8 kb standard temperature: 0 to +70c part number description part number description zgp323hsh4808 g 48-pin ssop 8k otp zgp323hss2808g 28-pin soic 8k otp zgp323hsp4008g 40-pin pdip 8k otp z gp323hsh2008g 20-pin ssop 8k otp zgp323hsh2808 g 28-pin ssop 8k otp zgp323hsp2008g 20-pin pdip 8k otp zgp323hsp2808g 28-pin pdip 8k otp z gp323hss2008g 20-pin soic 8k otp 8 kb extended temperature: ?40 to +105c part number description part number description zgp323heh4808 g 48-pin ssop 8k otp zgp323hes2808g 28-pin soic 8k otp zgp323hep4008g 40-pin pdip 8k otp z gp323heh2008g 20-pin ssop 8k otp zgp323heh2808 g 28-pin ssop 8k otp zgp323hep2008g 20-pin pdip 8k otp zgp323hep2808g 28-pin pdip 8k otp z gp323hes2008g 20-pin soic 8k otp 8 kb automotive temperature: ?40 to +125c part number description part number description zgp323hah4808 g 48-pin ssop 8k otp zgp323has2808g 28-pin soic 8k otp zgp323hap4008g 40-pin pdip 8k otp z gp323hah2008g 20-pin ssop 8k otp zgp323hah2808 g 28-pin ssop 8k otp zgp323hap2008g 20-pin pdip 8k otp zgp323hap2808g 28-pin pdip 8k otp z gp323has2008g 20-pin soic 8k otp
zgp323h product specification ps023806-0506 ordering information 93 4 kb standard temperature: 0 to +70c part number description part number description zgp323hsh4804g 48-pin ssop 4k otp zgp323hss2804g 28-pin soic 4k otp zgp323hsp4004g 40-pin pdip 4k otp zgp323hsh2004g 20-pin ssop 4k otp zgp323hsh2804g 28-pin ssop 4k otp zgp323hsp2004g 20-pin pdip 4k otp zgp323hsp2804g 28-pin pdip 4k otp zgp323hss2004g 20-pin soic 4k otp 4 kb extended temperature: ?40 to +105c part number description part number description zgp323heh4804g 48-pin ssop 4k otp zgp323hes2804g 28-pin soic 4k otp zgp323hep4004g 40-pin pdip 4k otp zgp323heh2004g 20-pin ssop 4k otp zgp323heh2804g 28-pin ssop 4k otp zgp323hep2004g 20-pin pdip 4k otp zgp323hep2804g 28-pin pdip 4k otp zgp323hes2004g 20-pin soic 4k otp 4 kb automotive temperature: ?40 to +125c part number description part number description zgp323hah4804g 48-pin ssop 4k otp zgp323has2804g 28-pin soic 4k otp zgp323hap4004g 40-pin pdip 4k otp zgp323hah2004g 20-pin ssop 4k otp zgp323hah2804g 28-pin ssop 4k otp zgp323hap2004g 20-pin pdip 4k otp zgp323hap2804g 28-pin pdip 4k otp ZGP323HAS2004G 20-pin soic 4k otp additional components part number description part number description visit the zilog web site at http://www.zilog.com/ for ordering information on additional com- ponents and development tools for the zgp323h.
zgp323h product specification ps023806-0506 ordering information 94 for fast results, contact your lo cal zilog sales office for assistance in ordering the part desired. codes zg = zilog general purpose family p = otp 323 = family designation h = high voltage t = temparature s = standard 0 to +70c e = extended -40 to +105c a = automotive -40 to +125c p = package type: k = cdip p = pdip h = ssop s = soic ## = number of pins cc = memory size m = molding compound g = green plastic molding compound e = standard cer dip flow
zgp323h product specification ps023806-0506 ordering information 95 example zg p 323 h t p 48 32 g molding compound memory size number of pins package type: e = cdip p = pdip h = ssop s = soic temperature: s = standard e = extended a = automotive voltage: h = high family designation otp zilog general-purpose family
zgp323h product specification ps023806-0506 document number description 96 document number description the document control number that appears in the footer of each page of this document contains unique identifying attributes, as indicated in the following table: ps product specification 0238 unique document number 06 revision number 0506 month and year published
zgp323h product specification ps023806-0506 customer support 97 customer support if you experience any problems while operating th is product, please check the zilog knowledge base: http://kb.zilog.co m/kb/okbmain.as p if you cannot find an answer or have further questio ns, please see the zilog technical support web page: http://support.zilog.com
zgp323h product specification ps023806-0506 index 98 index numerics 16-bit counter/timer circuits 40 20-pin dip package diagram 83 20-pin ssop package diagram 84 28-pin dip package diagram 86 28-pin soicpackage diagram 85 28-pin ssop package diagram 87 40-pin dip package diagram 87 48-pin ssop package diagram 89 8-bit counter/timer circuits 36 a absolute maximum ratings 73 ac characteristics 80 timing diagram 80 address spaces, basic 1 architecture 1 expanded register file 22 b basic address spaces 1 block diagram, zgp323h functional 3 c capacitance 74 characteristics ac 80 dc 74 clock 47 comparator inputs/outputs 18 configuration port 0 12 port 1 13 port 2 14 port 3 15 port 3 counter/timer 17 counter/timer 16-bit circuits 40 8-bit circuits 36 brown-out voltage/standby 58 clock 47 demodulation mode c ount capture flow- chart 38 demodulation mode flowchart 39 eprom selectable options 58 glitch filter circuitry 34 halt instruction 48 input circuit 34 interrupt block diagram 45 interrupt types, sources and vectors 46 oscillator configuration 47 output circuit 43 ping-pong mode 42 port configuration register 49 resets and wdt 57 sclk circuit 51 stop instruction 48 stop mode recovery register 51 stop mode recovery register 2 55 stop mode recovery source 53 t16 demodulation mode 41 t16 transmit mode 40 t16_out in modulo-n mode 41 t16_out in single-pass mode 41 t8 demodulation mode 37 t8 transmit mode 34 t8_out in modulo-n mode 37 t8_out in single-pass mode 37 transmit mode flowchart 35 voltage detection and flags 59 watch-dog timer mode register 56 watch-dog timer time select 57 ctr(d)01h t8 and t16 common functions
zgp323h product specification ps023806-0506 index 99 29 d dc characteristics 74 demodulation mode count capture flowchart 38 flowchart 39 t16 41 t8 37 description functional 19 general 3 pin 5 e eprom selectable options 58 expanded register file 20 expanded register file architecture 22 expanded register file control registers 64 flag 71 interrupt mask register 71 interrupt priority register 70 interrupt request register 70 port 0 and 1 mode register 69 port 2 configuration register 67 port 3 mode register 68 port configuration register 67 register pointer 72 stack pointer high register 72 stack pointer low register 72 stop-mode recove ry register 65 stop-mode recovery register 2 66 t16 control register 62 t8 and t16 common c ontrol functions reg- ister 61 t8/t16 control register 63 tc8 control register 59 watch-dog timer register 67 f features standby modes 2 functional description counter/timer func tional blocks 34 ctr(d)01h register 29 ctr0(d)00h register 27 ctr2(d)02h register 31 ctr3(d)03h register 33 expanded register file 20 expanded register file architecture 22 hi16(d)09h register 26 hi8(d)0bh register 26 l08(d)0ah register 26 l0i6(d)08h register 26 program memory map 20 ram 19 register description 58 register file 24 register pointer 23 register pointer detail 25 smr2(f)0d1h register 34 stack 25 tc16h(d)07h register 26 tc16l(d)06h register 27 tc8h(d)05h register 27 tc8l(d)04h register 27 g glitch filter circuitry 34 h halt instruction, counter/timer 48 i input circuit 34 interrupt block diagram, counter/timer 45 interrupt types, sources and vectors 46
zgp323h product specification ps023806-0506 index 100 l low-voltage detection register 58 m memory, program 19 modulo-n mode t16_out 41 t8_out 37 o oscillator configuration 47 output circuit, counter/timer 43 p package information 20-pin dip package diagram 83 20-pin ssop package diagram 84 28-pin dip package diagram 86 28-pin soic package diagram 85 28-pin ssop package diagram 87 40-pin dip package diagram 87 48-pin ssop package diagram 89 pin configuration 20-pin dip/soic/ssop 5 28-pin dip/soic/ssop 6 40- and 48-pin 8 40-pin dip 7 48-pin ssop 8 pin functions port 0 (p07 - p00) 11 port 0 (p17 - p10) 12 port 0 configuration 12 port 1 configuration 13 port 2 (p27 - p20) 13 port 2 (p37 - p30) 14 port 2 configuration 14 port 3 configuration 15 port 3 counter/timer configuration 17 reset) 18 xtal1 (time-based input 10 xtal2 (time-based output) 10 ping-pong mode 42 port 0 configuration 12 port 0 pin function 11 port 1 configuration 13 port 1 pin function 12 port 2 configuration 14 port 2 pin function 13 port 3 configuration 15 port 3 pin function 14 port 3counter/timer configuration 17 port configurati on register 49 power connections 1 power supply 5 program memory 19 map 20 r ratings, absolute maximum 73 register 55 ctr(d)01h 29 ctr0(d)00h 27 ctr2(d)02h 31 ctr3(d)03h 33 flag 71 hi16(d)09h 26 hi8(d)0bh 26 interrupt priority 70 interrupt request 70 interruptmask 71 l016(d)08h 26 l08(d)0ah 26 lvd(d)0ch 58 pointer 72 port 0 and 1 69 port 2 configuration 67 port 3 mode 68 port configuration 49, 67
zgp323h product specification ps023806-0506 index 101 smr2(f)0dh 34 stack pointer high 72 stack pointer low 72 stop mode recovery 51 stop mode recovery 2 55 stop-mode recovery 65 stop-mode recovery 2 66 t16 control 62 t8 and t16 common control functions 61 t8/t16 control 63 tc16h(d)07h 26 tc16l(d)06h 27 tc8 control 59 tc8h(d)05h 27 tc8l(d)04h 27 voltage detection 64 watch-dog timer 67 register description counter/timer2 ls-byte hold 27 counter/timer2 ms-byte hold 26 counter/timer8 control 27 counter/timer8 high hold 27 counter/timer8 low hold 27 ctr2 counter/timer 16 control 31 ctr3 t8/t16 control 33 stop mode recovery2 34 t16_capture_lo 26 t8 and t16 common functions 29 t8_capture_hi 26 t8_capture_lo 26 register file 24 expanded 20 register pointer 23 detail 25 reset pin function 18 resets and wdt 57 s sclk circuit 51 single-pass mode t16_out 41 t8_out 37 stack 25 standard test conditions 73 standby modes 2 stop instruction, counter/timer 48 stop mode recovery 2 register 55 source 53 stop mode recovery 2 55 stop mode recovery register 51 t t16 transmit mode 40 t16_capture_hi 26 t8 transmit mode 34 t8_capture_hi 26 test conditions, standard 73 test load diagram 74 timing diagram, ac 80 transmit mode flowchart 35 v vcc 5 voltage brown-out/standby 58 detection and flags 59 voltage detection register 64 w watch-dog timer mode registerwatch-dog timer mode regis- ter 56 time select 57 x xtal1 5
zgp323h product specification ps023806-0506 index 102 xtal1 pin function 10 xtal2 5 xtal2 pin function 10

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